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https://github.com/zannatul-naim/digital-system-design

Digital System Design Lab Codes using Verilog
https://github.com/zannatul-naim/digital-system-design

adder d-flipflop flipflop full-adder half-adder jk-flipflop ripple-carry-adder t-flipflop verilog

Last synced: 9 days ago
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Digital System Design Lab Codes using Verilog

Host: GitHub
URL: https://github.com/zannatul-naim/digital-system-design
Owner: Zannatul-Naim
Created: 2022-08-01T15:54:21.000Z (over 2 years ago)
Default Branch: main
Last Pushed: 2022-11-27T09:04:25.000Z (almost 2 years ago)
Last Synced: 2023-03-05T09:42:16.916Z (over 1 year ago)
Topics: adder, d-flipflop, flipflop, full-adder, half-adder, jk-flipflop, ripple-carry-adder, t-flipflop, verilog
Language: Verilog
Homepage:
Size: 52.7 KB
Stars: 2
Watchers: 1
Forks: 0
Open Issues: 0
Metadata Files:
- Readme: README.md

Awesome Lists containing this project

README

        # Digital-System-Design

Digital System Design Lab verilog codes

### Basic Gates

  - [OR GATE](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Basic_Gates/or_gate.v)

  - [AND GATE](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Basic_Gates/and_gate.v)

  - [NOT GATE](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Basic_Gates/not_gate.v)

  - [NAND GATE](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Basic_Gates/nand_gate.v)

  - [NOR GATE](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Basic_Gates/nor_gate.v)

  - [X-OR GATE](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Basic_Gates/xor_gate.v)

  - [X-NOR GATE](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Basic_Gates/xnor_gate.v)

### Code Converter

  - [Binary to Gray conversion](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Code-Converter/binary_to_gray.v)

  - [Gray to Binary conversion](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Code-Converter/gray_to_binary.v)

  - [BCD to Excess-3](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Code-Converter/bcd_to_excess3.v)

  - [Excess-3 to BCD](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Code-Converter/excess3_to_bcd.v)

### Adder

  - [Half Adder](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Adder/half_adder.v)

  - [Full Adder (using half adder)](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Adder/full_adder.v)

  - [Full Adder (without using half adder)](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Adder/fullAdder.v)

  - [4 Bit Ripple Carry Adder](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Adder/4_bit_ripple_carry_adder.v)

  - [4 Bit Carry Lookahead Adder](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Adder/carry_look_ahead_adder.v)

### Subtractor

  - [Half Subtractor](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Subtractor/half_subtractor.v)

  - [Full Subtractor](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Subtractor/full_subtractor.v)

### Adder-Subtractor

  - [4 bit adder subtractor](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Adder-Subtractor/adder_subtractor_4_bit.v)

  

### Comparator

  - [2 bit comparator](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Comparator/2_bit_comparator.v)

### Multiplexer

  - [2x1 MUX](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Multiplexer/2x1_multiplexer.v)

  - [Enable 2x1 MUX](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Multiplexer/enable_2x1_multiplexer.v)

  - [4x1 MUX](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Multiplexer/4x1_multiplexer.v)

  - [4x1 MUX using 2x1 MUX](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Multiplexer/4x1_mux_using_2x1.v)

  - [8x1 MUX](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Multiplexer/8x1_mux.v)

### Multiplier

  - [2x2 Array Multiplier](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Multiplier/2x2_multiplier.v) 

### Flip Flops

  - [JK FlipFlop](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/FlipFlops/jk_flipflop.v)

  - [D FlipFlop](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/FlipFlops/d_flipflop.v)

  - [D flipflop using SR flipflop with clear input](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/FlipFlops/d_flipflop_with_clear.v)

  - [T FlipFlop](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/FlipFlops/t_flipflop.v)

  - [Master Slave JK flipflop](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/FlipFlops/master_slave_jk_flipflp.v)

### Counters

  - Synchronous

    - [4 bit random sequence](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Counter/Synchronous/random_sequence_sync_counter_4_bit.v)

    - [3 Bit Synchronous Up/Down](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Counter/Synchronous/3_bit_Synchronous_up-down_counter.v)

    

  - Asynchronous

    - [4 bit ripple counter or mod-16 counter](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Counter/Asynchronous/4_bit_ripple_counter.v)

    - [Mod - 10 Counter](https://github.com/Zannatul-Naim/Digital-System-Design/blob/main/Counter/Asynchronous/mod_10_async.v)