CPLD-Guide

Complex Programmable Logic Device (CPLD) Guide
https://github.com/mikeroyal/CPLD-Guide

Last synced: 16 days ago
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OpenCL Tools, Libraries and Frameworks
- NVIDIA® Nsight™ Visual Studio Edition
- Radeon™ GPU Profiler
- Radeon™ GPU Analyzer
- AMD Radeon ProRender - based rendering engine that enables creative professionals to produce stunningly photorealistic images on virtually any GPU, any CPU, and any OS in over a dozen leading digital content creation and CAD applications.
- Intel® SDK For OpenCL™ Applications - intensive workloads. Customize heterogeneous compute applications and accelerate performance with kernel-based programming.
- NVIDIA cuDNN - accelerated library of primitives for [deep neural networks](https://developer.nvidia.com/deep-learning). cuDNN provides highly tuned implementations for standard routines such as forward and backward convolution, pooling, normalization, and activation layers. cuDNN accelerates widely used deep learning frameworks, including [Caffe2](https://caffe2.ai/), [Chainer](https://chainer.org/), [Keras](https://keras.io/), [MATLAB](https://www.mathworks.com/solutions/deep-learning.html), [MxNet](https://mxnet.incubator.apache.org/), [PyTorch](https://pytorch.org/), and [TensorFlow](https://www.tensorflow.org/).
- PV(ParaVirtualization) - assisted virtualization.
- Virtualized Infrastructure Manager (VIM)
- Management and Orchestration(MANO) - hosted initiative to develop an Open Source NFV Management and Orchestration (MANO) software stack aligned with ETSI NFV. Two of the key components of the ETSI NFV architectural framework are the NFV Orchestrator and VNF Manager, known as NFV MANO.
- OpenRAN - vendor deployments.
- Open vSwitch(OVS)
- Multi-access edge computing (MEC) - parties across multi-vendor Multi-access Edge Computing platforms.
- Cloud-Native Network Functions(CNF)
- Physical Network Function(PNF)
- Virtualization-based Security (VBS)
- Hypervisor-Enforced Code Integrity (HVCI) - V, uses hardware virtualization to protect kernel-mode processes against the injection and execution of malicious or unverified code. Code integrity validation is performed in a secure environment that is resistant to attack from malicious software, and page permissions for kernel mode are set and maintained by the hypervisor.
- KVM (for Kernel-based Virtual Machine) - V). It consists of a loadable kernel module, kvm.ko, that provides the core virtualization infrastructure and a processor specific module, kvm-intel.ko or kvm-amd.ko.
- Apple Hypervisor - party kernel extensions. Hypervisor provides C APIs so you can interact with virtualization technologies in user space, without writing kernel extensions (KEXTs). As a result, the apps you create using this framework are suitable for distribution on the [Mac App Store](https://www.appstore.com/).
- Apple Virtualization Framework - level APIs for creating and managing virtual machines on Apple silicon and Intel-based Mac computers. This framework is used to boot and run a Linux-based operating system in a custom environment that you define. It also supports the [Virtio specification](https://www.redhat.com/en/virtio-networking-series), which defines standard interfaces for many device types, including network, socket, serial port, storage, entropy, and memory-balloon devices.
- Apple Paravirtualized Graphics Framework - accelerated graphics for macOS running in a virtual machine, hereafter known as the guest. The operating system provides a graphics driver that runs inside the guest, communicating with the framework in the host operating system to take advantage of Metal-accelerated graphics.
- VMware Workstation
- Verdi® Protocol Analyzer
- Synopsys’ Verdi® HW SW Debug - driven SoC verification by providing a synchronized multi-window view of the design’s behavior of both hardware and software. It combines an instruction accurate embedded processor, RTL, C and assembly visibility for a comprehensive SoC debug solution.
- Synopsys Euclide - by-construction code development through context specific autocompletion and content assistance that is tuned for Synopsys VCS® simulation, Verdi® debug, and ZeBu® emulation, helping engineers to improve code quality during the entire project development cycle.
- Simvision - level and transaction-based flows across all IEEE-standard design, testbench, and assertion languages. It also supports concurrent visualization of hardware, software, and analog domains. It can be used to debug digital, analog, or mixed-signal designs written in Verilog, SystemVerilog, VHDL, and SystemC® languages or a combination thereof.
- Cadence® Palladium®
- Veloce Hardware-assisted Verification System - generation integrated circuit (IC) designs. It is the first complete, integrated offering that combines best-in-class virtual platform, hardware emulation, and Field Programmable Gate Array (FPGA) prototyping technologies and paves the way to leverage the latest powerful hardware-assisted verification methodologies.
- Synopsys ZeBu® EP1 - up, hybrid, hardware/software debug, simulation acceleration, performance validation and in-circuit emulation.
- SystemVerilog DPI (Direct Programming Interface)
- SystemVerilog Assertions
- SystemVerilog Functional Coverage
- Verilog-to-Routing (VTR) project - wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
- Verilog Power Estimation
- Cadence® SpeedBridge® Adapters - level testing. It's designed for pre-silicon RTL and integration of ASICs and systems on chip (SoCs), the solution can reproduce post-silicon bugs, as the design runs in the actual target system. The solution verifies emulated designs with the actual ASIC/SoC software/hardware, driver development, and application development, and runs with existing software and software test programs.
- Universal Verification Methodology (UVM) - testbench-acceleration).
- OpenCL ICD Loader
- clBLAS
- clFFT
- clSPARSE
- clRNG
- CLsmith - core environment, OpenCL. Its primary feature is the generation of random OpenCL kernels, exercising many features of the language. It also brings a novel idea of applying EMI, via dead-code injection.
- Oclgrind - races and barrier divergence, collecting instruction histograms, and for interactive OpenCL kernel debugging. The simulator is built on an interpreter for LLVM IR.
- NVIDIA Container Toolkit - container) and utilities to automatically configure containers to leverage NVIDIA GPUs.
- VirtManager
- HyperKit - level components such as the [VPNKit](https://github.com/moby/vpnkit) and [DataKit](https://github.com/moby/datakit). HyperKit currently only supports macOS using the [Hypervisor.framework](https://developer.apple.com/library/mac/documentation/DriversKernelHardware/Reference/Hypervisor/index.html) making it a core component of Docker Desktop for Mac.
- Intel® Graphics Virtualization Technology (Intel® GVT) - through, starting from 4th generation Intel Core (TM) processors with Intel processor graphics(Broadwell and newer). It can be used to virtualize the GPU for multiple guest virtual machines, effectively providing near-native graphics performance in the virtual machine and still letting your host use the virtualized GPU normally.
- Cloud Hypervisor - lang.org/) and is based on the [rust-vmm](https://github.com/rust-vmm) crates.
- Xen
- Ganeti
- Intel® SDK For OpenCL™ Applications - intensive workloads. Customize heterogeneous compute applications and accelerate performance with kernel-based programming.
- CLsmith - core environment, OpenCL. Its primary feature is the generation of random OpenCL kernels, exercising many features of the language. It also brings a novel idea of applying EMI, via dead-code injection.
- Edge
- GPUVerify
- Simvision - level and transaction-based flows across all IEEE-standard design, testbench, and assertion languages. It also supports concurrent visualization of hardware, software, and analog domains. It can be used to debug digital, analog, or mixed-signal designs written in Verilog, SystemVerilog, VHDL, and SystemC® languages or a combination thereof.
- Intel® SDK For OpenCL™ Applications - intensive workloads. Customize heterogeneous compute applications and accelerate performance with kernel-based programming.
- Packer
- Vagrant - to-use workflow and focus on automation, Vagrant lowers development environment setup time, increases production parity, and makes the "works on my machine" excuse a relic of the past. It provides easy to configure, reproducible, and portable work environments built on top of industry-standard technology and controlled by a single consistent workflow to help maximize the productivity and flexibility of you and your team.
- VMware vSphere Hypervisor - metal hypervisor that virtualizes servers; allowing you to consolidate your applications while saving time and money managing your IT infrastructure.
- VMware Workstation
- Hyper-V
- Veloce Hardware-assisted Verification System - generation integrated circuit (IC) designs. It is the first complete, integrated offering that combines best-in-class virtual platform, hardware emulation, and Field Programmable Gate Array (FPGA) prototyping technologies and paves the way to leverage the latest powerful hardware-assisted verification methodologies.
Verilog/SystemVerilog Learning Resources
Verilog/SystemVerilog Tools
- Icestudio
- PlatformIO - in. It provides support for multiplatforms and frameworks such as IoT, Arduino, CMSIS, ESP-IDF, FreeRTOS, libOpenCM3, mbed OS, Pulp OS, SPL, STM32Cube, Zephyr RTOS, ARM, AVR, Espressif (ESP8266/ESP32), FPGA, MCS-51 (8051), MSP430, Nordic (nRF51/nRF52), NXP i.MX RT, PIC32, RISC-V.
- PlatformIO for VSCode
- Chisel - lang.org/) programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog.
- Verilog to Routing(VTR) - source framework for conducting FPGA architecture and CAD Research & Development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
- Apio - built packages, project configuration tools and easy command interface to verify, synthesize, simulate and upload your verilog designs.
- IceStorm
- OpenTimer - Performance Timing Analysis Tool for VLSI Systems.
- EDA Playground
- Cascade - In-Time Compiler for Verilog from VMware Research. Cascade executes code immediately in a software simulator, and performs compilation in the background. When compilation is finished, the code is moved into hardware, and from the user’s perspective it simply gets faster over time.

Programming Languages

C 10 C++ 10 Python 5 Rust 4 MATLAB 3 C# 2 Verilog 2 HTML 1 Java 1 CMake 1

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Tools

Indexes

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CPLD-Guide

OpenCL Tools, Libraries and Frameworks

Verilog/SystemVerilog Learning Resources

Verilog/SystemVerilog Tools