https://github.com/alexforencich/verilog-axis

Verilog AXI stream components for FPGA implementation
https://github.com/alexforencich/verilog-axis

Last synced: 4 days ago
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Verilog AXI stream components for FPGA implementation

• Host: GitHub
• URL: https://github.com/alexforencich/verilog-axis
• Owner: alexforencich
• License: mit
• Created: 2014-11-06T00:17:52.000Z (over 10 years ago)
• Default Branch: master
• Last Pushed: 2024-08-07T04:11:51.000Z (8 months ago)
• Last Synced: 2024-08-07T12:23:36.242Z (8 months ago)
• Language: Python
• Homepage:
• Size: 1.14 MB
• Stars: 696
• Watchers: 47
• Forks: 216
• Open Issues: 16
• Metadata Files:
  • Readme: README
  • License: COPYING
  • Authors: AUTHORS

Awesome Lists containing this project

• ASIC-Design-Roadmap - ALEX FORENCICH - AXIS - axis) - Collection of AXI Stream bus components. Most components are fully parametrizable in interface widths. (Projects and IPs / Communication Technology)
• awesome-opensource-hardware - verilog-axis
• awesome-digital-ic - ALEX FORENCICH - AXIS - axis) - Collection of AXI Stream bus components. Most components are fully parametrizable in interface widths. (Projects and IPs / Communication Technology)

README