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https://github.com/pConst/basic_verilog
Must-have verilog systemverilog modules
https://github.com/pConst/basic_verilog
altera debounce delay encoder fifo fpga hls pwm spi-interface spi-master synchronizer tcl uart uart-controller uart-protocol uart-receiver uart-tx uart-verilog verilog xilinx
Last synced: about 1 month ago
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Must-have verilog systemverilog modules
- Host: GitHub
- URL: https://github.com/pConst/basic_verilog
- Owner: pConst
- Created: 2015-12-14T18:09:40.000Z (over 8 years ago)
- Default Branch: master
- Last Pushed: 2024-07-06T07:59:04.000Z (2 months ago)
- Last Synced: 2024-07-16T18:58:42.377Z (about 2 months ago)
- Topics: altera, debounce, delay, encoder, fifo, fpga, hls, pwm, spi-interface, spi-master, synchronizer, tcl, uart, uart-controller, uart-protocol, uart-receiver, uart-tx, uart-verilog, verilog, xilinx
- Language: Verilog
- Homepage:
- Size: 54.2 MB
- Stars: 1,489
- Watchers: 58
- Forks: 344
- Open Issues: 0
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Metadata Files:
- Readme: README.md
- License: license/88x31.png
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