https://github.com/doniagameel/verilog-adders-with-synthesis-using-oasys

explore different implementations of adders and study their characteristics.

carry-bypass-adder carry-increment-adder carry-look-ahead-adder carry-save-adder carry-select-adder carry-skip-adder floating-point-adder oasys ripple-carry-adder

Last synced: 07 Apr 2025