https://github.com/atticusrussell/mips

A pipelined MIPS microprocessor written in VHDL and simulated in Xilinx Vivado targeting Basys3 board. Simplified MIPS instruction set. Made in RIT DSD2 (CMPE-260).

clock-speed dsd2 fpga mips processor vhdl vivado

Last synced: 08 Feb 2026