Projects in Awesome Lists tagged with fpga

https://github.com/openwall/john

John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs

assembler c cracker crypt fpga gpgpu gpu hash john jtr mpi opencl openmp password ripper simd

Last synced: 16 Dec 2025

https://github.com/magnumripper/johntheripper

John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs

assembler c cracker crypt fpga gpgpu gpu hash john jtr mpi opencl openmp password ripper simd

Last synced: 09 Mar 2025

https://github.com/paddlepaddle/paddle-lite

PaddlePaddle High Performance Deep Learning Inference Engine for Mobile and Edge (飞桨高性能深度学习端侧推理引擎）

arm baidu deep-learning embedded fpga mali mdl mobile mobile-deep-learning neural-network

Last synced: 12 May 2025

https://github.com/PaddlePaddle/Paddle-Lite

PaddlePaddle High Performance Deep Learning Inference Engine for Mobile and Edge (飞桨高性能深度学习端侧推理引擎）

arm baidu deep-learning embedded fpga mali mdl mobile mobile-deep-learning neural-network

Last synced: 20 Mar 2025

https://github.com/logisim-evolution/logisim-evolution

Digital logic design tool and simulator

circuit circuits digital-circuit digital-circuits digital-logic digital-logic-design education fpga logic logisim logisim-evolution simulator timing-diagram verilog vhdl

Last synced: 15 Feb 2026

https://github.com/open-sdr/openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

802-11 ad9361 analog-devices csma dma fpga hardware hls ieee80211 linux mac80211 ofdm openwifi sdr software-defined-radio verilog wifi xilinx xilinx-fpga zynq

Last synced: 13 May 2025

https://github.com/LeiWang1999/FPGA

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga pynq verilog vivado xilinx

Last synced: 14 Mar 2025

https://github.com/leiwang1999/fpga

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga pynq verilog vivado xilinx

Last synced: 27 Jan 2026

https://github.com/enjoy-digital/litex

Build your hardware, easily!

fpga hardware system-on-chip

Last synced: 12 May 2025

https://github.com/hyperdbg/hyperdbg

State-of-the-art native debugging tools

binary-analysis chip debug debugger debugging debugging-tool ept fpga hardware hook hwdbg hyperdbg hypervisor kernel-debugger logic-analyzer malware-analysis reverse-engineering security security-tools windows-kernel

Last synced: 10 Jun 2026

https://github.com/HyperDbg/HyperDbg

State-of-the-art native debugging tools

binary-analysis chip debug debugger debugging debugging-tool ept fpga hardware hook hwdbg hyperdbg hypervisor kernel-debugger logic-analyzer malware-analysis reverse-engineering security security-tools windows-kernel

Last synced: 08 Apr 2025

https://github.com/SpinalHDL/VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga riscv soc softcore spinalhdl verilog vhdl

Last synced: 14 Mar 2025

https://github.com/spinalhdl/vexriscv

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga riscv soc softcore spinalhdl verilog vhdl

Last synced: 14 May 2025

https://github.com/openhwgroup/cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

ariane asic cpu fpga risc-v rv64gc systemverilog-hdl

Last synced: 13 May 2025

https://github.com/darklife/darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

core fpga risc-v riscv verilog

Last synced: 10 Feb 2026

https://github.com/jbush001/nyuziprocessor

GPGPU microprocessor architecture

fpga gpu gpu-computing graphics hardware microprocessor processor-architecture verilog

Last synced: 15 May 2025

https://github.com/stnolting/neorv32

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

asic cpu fpga microcontroller processor risc-v soc soft-core verilog vhdl

Last synced: 03 Apr 2026

https://github.com/jbush001/NyuziProcessor

GPGPU microprocessor architecture

fpga gpu gpu-computing graphics hardware microprocessor processor-architecture verilog

Last synced: 14 Mar 2025

https://github.com/glasgowembedded/glasgow

Scots Army Knife for electronics

debugging-tool fpga hardware usb

Last synced: 14 May 2025

https://github.com/GlasgowEmbedded/glasgow

Scots Army Knife for electronics

debugging-tool fpga hardware usb

Last synced: 03 Apr 2025

https://github.com/analogdevicesinc/hdl

HDL libraries and projects

analog-devices fpga hacktoberfest hdl jesd204b verilog

Last synced: 27 Feb 2026

https://github.com/corundum/corundum

Open source FPGA-based NIC and platform for in-network compute

fpga in-network-compute linux networking nic

Last synced: 15 May 2025

https://github.com/pconst/basic_verilog

Must-have verilog systemverilog modules

altera debounce delay encoder fifo fpga hls pwm spi-interface spi-master synchronizer tcl uart uart-controller uart-protocol uart-receiver uart-tx uart-verilog verilog xilinx

Last synced: 27 Jan 2026

https://github.com/spinalhdl/spinalhdl

Scala based HDL

fpga rtl scala verilog vhdl

Last synced: 13 May 2025

https://github.com/fpgawars/icestudio

:snowflake: Visual editor for open FPGA boards

blocks editor fpga icestorm icestudio ide javascript lattice verilog

Last synced: 14 May 2025

https://github.com/FPGAwars/icestudio

:snowflake: Visual editor for open FPGA boards

blocks editor fpga icestorm icestudio ide javascript lattice verilog

Last synced: 30 Mar 2025

https://github.com/olofk/serv

SERV - The SErial RISC-V CPU

asic fpga risc-v verilog

Last synced: 25 Feb 2026

https://github.com/SpinalHDL/SpinalHDL

Scala based HDL

fpga rtl scala verilog vhdl

Last synced: 15 Mar 2025

https://github.com/amaranth-lang/amaranth

A modern hardware definition language and toolchain based on Python

amaranth-hdl fpga hdl

Last synced: 13 May 2025

https://github.com/pConst/basic_verilog

Must-have verilog systemverilog modules

altera debounce delay encoder fifo fpga hls pwm spi-interface spi-master synchronizer tcl uart uart-controller uart-protocol uart-receiver uart-tx uart-verilog verilog xilinx

Last synced: 14 Mar 2025

https://github.com/riscv-mcu/e203_hbirdv2

The Ultra-Low Power RISC-V Core

china core cpu e203 fpga hummingbird low-power nuclei risc-v riscv soc verilog

Last synced: 27 Jan 2026

https://github.com/clash-lang/clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

asic fpga hardware-description-language haskell systemverilog verilog vhdl

Last synced: 14 May 2025

https://github.com/pulp-platform/axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asic axi axi4 axi4-lite fpga hardware ip network-on-chip rtl systemverilog

Last synced: 07 Mar 2026

https://github.com/fastmachinelearning/hls4ml

Machine learning on FPGAs using HLS

fpga hls intel-hls keras machine-learning neural-network onnx python pytorch vivado vivado-hls

Last synced: 12 Dec 2025

https://github.com/ultraembedded/riscv

RISC-V CPU Core (RV32IM)

asic cpu fpga pipeline-processor risc-v riscv-linux rv32i rv32im verification verilator verilog

Last synced: 26 Jan 2026

https://github.com/xilinx/brevitas

Brevitas: neural network quantization in PyTorch

brevitas deep-learning fpga hardware-acceleration neural-networks ptq pytorch qat quantization xilinx

Last synced: 11 Oct 2025

https://github.com/xilinx/vitis-tutorials

Vitis In-Depth Tutorials

aiengine alveo alveo-u200 alveo-u250 embedded embedded-systems fpga kria kria-som vitis xrt zcu102 zcu104

Last synced: 14 May 2025

https://github.com/sylefeb/Silice

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

fpga language programming

Last synced: 21 Apr 2025

https://github.com/trabucayre/openfpgaloader

Universal utility for programming FPGA

arty bitstream cyclone fpga gowin intel lattice trenz-gowin-littlebee xilinx

Last synced: 14 May 2025

https://github.com/Xilinx/brevitas

Brevitas: neural network quantization in PyTorch

brevitas deep-learning fpga hardware-acceleration neural-networks ptq pytorch qat quantization xilinx

Last synced: 23 Apr 2025

https://github.com/ZipCPU/zipcpu

A small, light weight, RISC CPU soft core

cpu cross-compiler fpga risc-cpu soft-core verilator verilog wishbone wishbone-bus zipcpu

Last synced: 14 Mar 2025

https://github.com/platformio/platformio-vscode-ide

PlatformIO IDE for VSCode: The next generation integrated development environment for IoT

debugger embedded fpga hardware iot microcontroller platformio verilog vscode

Last synced: 14 May 2025

https://github.com/olofk/fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

eda fpga package-manager python reuse verilog vhdl

Last synced: 13 May 2025

https://github.com/doonny/PipeCNN

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

altera-opencl-sdk deep-learning deep-neural-networks fpga fpga-accelerator hardware hls opencl

Last synced: 15 Mar 2025

https://github.com/hdl-util/hdmi

Send video/audio over HDMI on an FPGA

altera audio dvi fpga hdlmake hdmi intel quartus systemverilog video vivado xilinx

Last synced: 25 Jan 2026

https://github.com/ettusresearch/uhd

The USRP™ Hardware Driver Repository

driver fpga sdr uhd usrp

Last synced: 08 Apr 2026

https://github.com/trabucayre/openFPGALoader

Universal utility for programming FPGA

arty bitstream cyclone fpga gowin intel lattice trenz-gowin-littlebee xilinx

Last synced: 26 Mar 2025

https://github.com/cariboulabs/cariboulite

CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR

defined fpga ice40 icestorm pi radio raspberry rf rpi sdr software yosys

Last synced: 14 May 2025

https://github.com/siliconcompiler/siliconcompiler

Modular hardware build system

asic cmos eda fpga hls make rtl synthesis verilog vhdl

Last synced: 11 May 2026

https://github.com/EttusResearch/uhd

The USRP™ Hardware Driver Repository

driver fpga sdr uhd usrp

Last synced: 22 Apr 2025

https://github.com/hukenovs/dsp-theory

Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc.

convolution digital-signal-processing dsp fast-fourier-transform fft finite-impulse-response fir fpga lectures lessons numpy numpy-tutorial python scipy tutorial

Last synced: 16 May 2025

https://github.com/greatscottgadgets/luna

Amaranth HDL framework for monitoring, hacking, and developing USB devices

fpga hardware usb

Last synced: 14 May 2025

https://github.com/oneapi-src/oneapi-samples

Samples for Intel® oneAPI Toolkits

ai cpu cuda fortran fpga gpu jupyter oneapi oneccl onedal onednn onedpl onemkl onetbb python pytorch rendering scikit-learn sycl tensorflow

Last synced: 10 Apr 2025

https://github.com/firesim/firesim

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

boom cloud datacenter firesim fpga hardware on-prem risc-v rocket-chip simulation

Last synced: 30 May 2026

https://github.com/oneapi-src/oneAPI-samples

Samples for Intel® oneAPI Toolkits

ai cpu cuda fortran fpga gpu jupyter oneapi oneccl onedal onednn onedpl onemkl onetbb python pytorch rendering scikit-learn sycl tensorflow

Last synced: 20 Mar 2025

https://github.com/ultraembedded/biriscv

32-bit Superscalar RISC-V CPU

artix-7 asic branch-prediction coremark cpu fpga in-order linux pipelined-processors risc-v riscv-linux rv32i rv32im superscalar verilator verilog xilinx

Last synced: 04 Apr 2025

https://github.com/fpgawars/apio

:seedling: Open source ecosystem for open FPGA boards

apio cli fpga icestorm lattice manager package python verilog

Last synced: 15 May 2026

https://github.com/verilog-to-routing/vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

cad eda fpga placement routing synthesis verilog vpr vtr

Last synced: 14 Mar 2025

https://github.com/circuitvalley/USB_C_Industrial_Camera_FPGA_USB3

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

camera csi fpga mipi mipi-csi-receiver usb usb3 uvc verilog

Last synced: 02 Apr 2025

https://github.com/eugene-tarassov/vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

arty-a7 boom fpga genesys2 kc705 linux nexys-video risc-v riscv rocketchip vc707 vivado xilinx

Last synced: 22 Apr 2025

https://github.com/chipsalliance/cores-veer-eh1

VeeR EH1 core

ahb-lite asic-design axi4 fpga fusesoc open-source-hardware processor risc risc-v riscv riscv32 rtl veer verilator western-digital

Last synced: 08 Feb 2026

https://github.com/circuitvalley/usb_c_industrial_camera_fpga_usb3

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

camera csi fpga mipi mipi-csi-receiver usb usb3 uvc verilog

Last synced: 26 Jan 2026

https://github.com/xilinx/finn

Dataflow compiler for QNN inference on FPGAs

compiler dataflow fpga neural-network quantization

Last synced: 11 Oct 2025

https://github.com/riscvarchive/riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

asic fpga open-isa risc-v socs

Last synced: 22 Apr 2025

https://github.com/FPGAwars/apio

:seedling: Open source ecosystem for open FPGA boards

apio cli fpga icestorm lattice manager package python verilog

Last synced: 22 Apr 2025

https://github.com/chipsalliance/Cores-VeeR-EH1

VeeR EH1 core

ahb-lite asic-design axi4 fpga fusesoc open-source-hardware processor risc risc-v riscv riscv32 rtl veer verilator western-digital

Last synced: 22 Apr 2025

https://github.com/LNIS-Projects/OpenFPGA

An Open-source FPGA IP Generator

fpga fpga-soc

Last synced: 07 Mar 2025

https://github.com/lnis-uofu/OpenFPGA

An Open-source FPGA IP Generator

fpga fpga-soc

Last synced: 14 Mar 2025

https://github.com/obijuan/open-fpga-verilog-tutorial

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

fpga fpgawars icestorm lattice linux openfpga verilog

Last synced: 13 Apr 2025

https://github.com/f4pga/prjxray

Documenting the Xilinx 7-series bit-stream format.

artix artix7 bitstream fpga fuzzer kintex7 symbiflow toolchain tools vivado xilinx xilinx-fpga

Last synced: 22 Apr 2025

https://github.com/Cr4sh/s6_pcie_microblaze

PCI Express DIY hacking toolkit for Xilinx SP605. This repository is also home of Hyper-V Backdoor and Boot Backdoor, check readme for links and info

backdoor dma fpga hyper-v hypervisor kernel microblaze pci-e rootkit uefi xilinx

Last synced: 10 Apr 2025

https://github.com/cr4sh/s6_pcie_microblaze

PCI Express DIY hacking toolkit for Xilinx SP605. This repository is also home of Hyper-V Backdoor and Boot Backdoor, check readme for links and info

backdoor dma fpga hyper-v hypervisor kernel microblaze pci-e rootkit uefi xilinx

Last synced: 12 Apr 2025

https://github.com/VUnit/vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

asic fpga systemverilog-hdl testbench unit-testing universal-verification-methodology verification verilog-hdl vhdl

Last synced: 18 Apr 2025

https://github.com/romeric/Fastor

A lightweight high performance tensor algebra framework for modern C++

fpga hpc multidimensional-arrays simd small-blas tensor-contraction tensors

Last synced: 27 Apr 2025

https://github.com/ultraembedded/cores

Various HDL (Verilog) IP Cores

asic audio fpga i2s rtl sdram spi sram uart usb verilator verilog verilog-components verilog-hdl

Last synced: 25 Jan 2026

https://github.com/open-sdr/openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

ad9361 analog-devices csma dma fpga hardware hls ieee80211 linux mac80211 ofdm rtl sdr software-defined-radio verilog vhdl wi-fi xilinx zynq

Last synced: 15 May 2025

https://github.com/Xilinx/finn

Dataflow compiler for QNN inference on FPGAs

compiler dataflow fpga neural-network quantization

Last synced: 20 Mar 2025

https://github.com/xupsh/pp4fpgas-cn

中文版 Parallel Programming for FPGAs

fpga hls parallel-programming pynq

Last synced: 09 Mar 2026

https://github.com/konosubakonoakua/fpga_mcu_debugger_collections

各种LInk大合集

altiumdeisgner bootloader cmsis-dap daplink debugger digilent diy fpga ftdi jlink mcu pcb stlink stm32

Last synced: 13 Apr 2026

https://github.com/olofk/edalize

An abstraction library for interfacing EDA tools

altera eda fossi fpga ghdl icarus-verilog icestorm lattice modelsim riviera-pro simulation spyglass synthesis systemverilog verilator verilog vhdl vivado xilinx yosys

Last synced: 14 May 2025

https://github.com/m-labs/nmigen

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

fpga hdl nmigen yosys

Last synced: 04 Apr 2025

https://github.com/emsec/hal

HAL – The Hardware Analyzer

embedded-security fpga hal hardware integrated-circuits netlist reverse-engineering security

Last synced: 15 May 2025

https://github.com/fpgasystems/fpga-network-stack

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

100gbit fpga network roce tcp

Last synced: 21 Apr 2025

https://github.com/juliankemmerer/pipelinec

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

c fpga fpga-acceleration fpga-accelerators fpga-programming hardware hardware-description hardware-description-language high-level-synthesis hls open-source-hardware pipelines python vhdl

Last synced: 15 May 2025

https://github.com/JulianKemmerer/PipelineC

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

c fpga fpga-acceleration fpga-accelerators fpga-programming hardware hardware-description hardware-description-language high-level-synthesis hls open-source-hardware pipelines python vhdl

Last synced: 22 Apr 2025

https://github.com/princetonuniversity/openpiton

The OpenPiton Platform

fpga processor python research-platform verilog

Last synced: 16 May 2025

https://github.com/WangXuan95/FPGA-USB-Device

An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。

cdc fpga keyboard rtl usb usb-audio usb-camera usb-cdc usb-controller usb-device usb-disk usb-hid usb-keyboard usb-microphone usb-serial usb-speaker usb-uart usb-uvc uvc verilog

Last synced: 22 Apr 2025

https://github.com/xilinx/xrt

Run Time for AIE and FPGA based platforms

fpga linux-kernel vitis xrt

Last synced: 10 Feb 2026

https://github.com/Xilinx/XRT

Run Time for AIE and FPGA based platforms

fpga linux-kernel vitis xrt

Last synced: 21 Apr 2025

https://github.com/nickg/nvc

VHDL compiler and simulator

compiler fpga simulator vhdl

Last synced: 14 Mar 2026

https://github.com/VLSI-EDA/PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

altera asic fpga hardware-designs hardware-libraries hardware-modules lattice osvvm poc-library python regression-testing simulation synthesis testbenches uvvm verification vhdl vlsi vunit xilinx