Projects in Awesome Lists tagged with fpga

https://github.com/openwall/john

John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs

assembler c cracker crypt fpga gpgpu gpu hash john jtr mpi opencl openmp password ripper simd

Last synced: 01 Oct 2024

https://github.com/magnumripper/JohnTheRipper

John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs

assembler c cracker crypt fpga gpgpu gpu hash john jtr mpi opencl openmp password ripper simd

Last synced: 14 Aug 2024

https://github.com/paddlepaddle/paddle-lite

PaddlePaddle High Performance Deep Learning Inference Engine for Mobile and Edge (飞桨高性能深度学习端侧推理引擎）

arm baidu deep-learning embedded fpga mali mdl mobile mobile-deep-learning neural-network

Last synced: 25 Sep 2024

https://github.com/PaddlePaddle/Paddle-Lite

PaddlePaddle High Performance Deep Learning Inference Engine for Mobile and Edge (飞桨高性能深度学习端侧推理引擎）

arm baidu deep-learning embedded fpga mali mdl mobile mobile-deep-learning neural-network

Last synced: 31 Jul 2024

https://github.com/logisim-evolution/logisim-evolution

Digital logic design tool and simulator

circuit circuits digital-circuit digital-circuits digital-logic digital-logic-design education fpga logic logisim logisim-evolution simulator timing-diagram verilog vhdl

Last synced: 30 Sep 2024

https://github.com/leiwang1999/fpga

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga pynq verilog vivado xilinx

Last synced: 30 Sep 2024

https://github.com/open-sdr/openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

802-11 ad9361 analog-devices csma dma fpga hardware hls ieee80211 linux mac80211 ofdm openwifi sdr software-defined-radio verilog wifi xilinx xilinx-fpga zynq

Last synced: 26 Sep 2024

https://github.com/LeiWang1999/FPGA

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga pynq verilog vivado xilinx

Last synced: 30 Jul 2024

https://github.com/enjoy-digital/litex

Build your hardware, easily!

fpga hardware system-on-chip

Last synced: 30 Sep 2024

https://github.com/HyperDbg/HyperDbg

State-of-the-art native debugging tool

binary-analysis chip debug debugger debugging debugging-tool ept fpga hardware hook hwdbg hyperdbg hypervisor kernel-debugger logic-analyzer malware-analysis reverse-engineering security security-tools windows-kernel

Last synced: 01 Aug 2024

https://github.com/hyperdbg/hyperdbg

State-of-the-art native debugging tool

binary-analysis chip debug debugger debugging debugging-tool ept fpga hardware hook hwdbg hyperdbg hypervisor kernel-debugger logic-analyzer malware-analysis reverse-engineering security security-tools windows-kernel

Last synced: 01 Oct 2024

https://github.com/SpinalHDL/VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga riscv soc softcore spinalhdl verilog vhdl

Last synced: 30 Jul 2024

https://github.com/darklife/darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

core cpu fpga processor processor-design risc-v riscv rtl rv32e rv32i softcore verilog

Last synced: 01 Oct 2024

https://github.com/openhwgroup/cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

ariane asic cpu fpga risc-v rv64gc systemverilog-hdl

Last synced: 30 Sep 2024

https://github.com/jbush001/nyuziprocessor

GPGPU microprocessor architecture

fpga gpu gpu-computing graphics hardware microprocessor processor-architecture verilog

Last synced: 30 Sep 2024

https://github.com/jbush001/NyuziProcessor

GPGPU microprocessor architecture

fpga gpu gpu-computing graphics hardware microprocessor processor-architecture verilog

Last synced: 30 Jul 2024

https://github.com/glasgowembedded/glasgow

Scots Army Knife for electronics

debugging-tool fpga hardware usb

Last synced: 30 Sep 2024

https://github.com/GlasgowEmbedded/glasgow

Scots Army Knife for electronics

debugging-tool fpga hardware usb

Last synced: 01 Aug 2024

https://github.com/fpgawars/icestudio

:snowflake: Visual editor for open FPGA boards

blocks editor fpga icestorm icestudio ide javascript lattice verilog

Last synced: 30 Sep 2024

https://github.com/FPGAwars/icestudio

:snowflake: Visual editor for open FPGA boards

blocks editor fpga icestorm icestudio ide javascript lattice verilog

Last synced: 01 Aug 2024

https://github.com/corundum/corundum

Open source FPGA-based NIC and platform for in-network compute

fpga in-network-compute linux networking nic

Last synced: 30 Sep 2024

https://github.com/spinalhdl/spinalhdl

Scala based HDL

fpga rtl scala verilog vhdl

Last synced: 30 Sep 2024

https://github.com/pconst/basic_verilog

Must-have verilog systemverilog modules

altera debounce delay encoder fifo fpga hls pwm spi-interface spi-master synchronizer tcl uart uart-controller uart-protocol uart-receiver uart-tx uart-verilog verilog xilinx

Last synced: 30 Sep 2024

https://github.com/SpinalHDL/SpinalHDL

Scala based HDL

fpga rtl scala verilog vhdl

Last synced: 30 Jul 2024

https://github.com/pConst/basic_verilog

Must-have verilog systemverilog modules

altera debounce delay encoder fifo fpga hls pwm spi-interface spi-master synchronizer tcl uart uart-controller uart-protocol uart-receiver uart-tx uart-verilog verilog xilinx

Last synced: 30 Jul 2024

https://github.com/amaranth-lang/amaranth

A modern hardware definition language and toolchain based on Python

amaranth-hdl fpga hdl

Last synced: 30 Sep 2024

https://github.com/stnolting/neorv32

:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

asic asip cpu embedded fpga gdb microcontroller neorv32 openocd processor risc-v riscv rtl rv32 safety soc soft-core system-on-chip verilog vhdl

Last synced: 31 Jul 2024

https://github.com/analogdevicesinc/hdl

HDL libraries and projects

analog-devices fpga hacktoberfest hdl jesd204b verilog

Last synced: 30 Sep 2024

https://github.com/olofk/serv

SERV - The SErial RISC-V CPU

asic fpga risc-v verilog

Last synced: 30 Sep 2024

https://github.com/clash-lang/clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

asic fpga hardware-description-language haskell systemverilog verilog vhdl

Last synced: 30 Sep 2024

https://github.com/sylefeb/Silice

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

fpga language programming

Last synced: 02 Aug 2024

https://github.com/ZipCPU/zipcpu

A small, light weight, RISC CPU soft core

cpu cross-compiler fpga risc-cpu soft-core verilator verilog wishbone wishbone-bus zipcpu

Last synced: 30 Jul 2024

https://github.com/ultraembedded/riscv

RISC-V CPU Core (RV32IM)

asic cpu fpga pipeline-processor risc-v riscv-linux rv32i rv32im verification verilator verilog

Last synced: 30 Sep 2024

https://github.com/riscv-mcu/e203_hbirdv2

The Ultra-Low Power RISC-V Core

china core cpu e203 fpga hummingbird low-power nuclei risc-v riscv soc verilog

Last synced: 30 Sep 2024

https://github.com/xilinx/vitis-tutorials

Vitis In-Depth Tutorials

aiengine alveo alveo-u200 alveo-u250 embedded embedded-systems fpga kria kria-som vitis xrt zcu102 zcu104

Last synced: 01 Oct 2024

https://github.com/doonny/PipeCNN

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

altera-opencl-sdk deep-learning deep-neural-networks fpga fpga-accelerator hardware hls opencl

Last synced: 30 Jul 2024

https://github.com/olofk/fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

eda fpga package-manager python reuse verilog vhdl

Last synced: 25 Sep 2024

https://github.com/platformio/platformio-vscode-ide

PlatformIO IDE for VSCode: The next generation integrated development environment for IoT

debugger embedded fpga hardware iot microcontroller platformio verilog vscode

Last synced: 30 Sep 2024

https://github.com/Xilinx/brevitas

Brevitas: neural network quantization in PyTorch

brevitas deep-learning fpga hardware-acceleration neural-networks ptq pytorch qat quantization xilinx

Last synced: 02 Aug 2024

https://github.com/beehive-lab/tornadovm

TornadoVM: A practical and efficient heterogeneous programming framework for managed languages

ai artificial-intelligence cuda fpga gpgpu gpu-acceleration gpu-computing gpus graalvm high-performance java java-library-acceleration level-zero-gpu-runtime levelzero multi-core opencl spirv tornadovm

Last synced: 25 Sep 2024

https://github.com/beehive-lab/TornadoVM

TornadoVM: A practical and efficient heterogeneous programming framework for managed languages

ai artificial-intelligence cuda fpga gpgpu gpu-acceleration gpu-computing gpus graalvm high-performance java java-library-acceleration level-zero-gpu-runtime levelzero multi-core opencl spirv tornadovm

Last synced: 01 Aug 2024

https://github.com/fastmachinelearning/hls4ml

Machine learning on FPGAs using HLS

fpga hls intel-hls keras machine-learning neural-network onnx python pytorch vivado vivado-hls

Last synced: 27 Sep 2024

https://github.com/cariboulabs/cariboulite

CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR

defined fpga ice40 icestorm pi radio raspberry rf rpi sdr software yosys

Last synced: 26 Sep 2024

https://github.com/hdl-util/hdmi

Send video/audio over HDMI on an FPGA

altera audio dvi fpga hdlmake hdmi intel quartus systemverilog video vivado xilinx

Last synced: 25 Sep 2024

https://github.com/trabucayre/openFPGALoader

Universal utility for programming FPGA

arty bitstream cyclone fpga gowin intel lattice trenz-gowin-littlebee xilinx

Last synced: 31 Jul 2024

https://github.com/hukenovs/dsp-theory

Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc.

convolution digital-signal-processing dsp fast-fourier-transform fft finite-impulse-response fir fpga lectures lessons numpy numpy-tutorial python scipy tutorial

Last synced: 30 Sep 2024

https://github.com/verilog-to-routing/vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

cad eda fpga placement routing synthesis verilog vpr vtr

Last synced: 30 Jul 2024

https://github.com/EttusResearch/uhd

The USRP™ Hardware Driver Repository

driver fpga sdr uhd usrp

Last synced: 02 Aug 2024

https://github.com/pulp-platform/axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asic axi axi4 axi4-lite fpga hardware ip network-on-chip rtl systemverilog

Last synced: 30 Jul 2024

https://github.com/oneapi-src/oneapi-samples

Samples for Intel® oneAPI Toolkits

ai cpu cuda fortran fpga gpu jupyter oneapi oneccl onedal onednn onedpl onemkl onetbb python pytorch rendering scikit-learn sycl tensorflow

Last synced: 26 Sep 2024

https://github.com/greatscottgadgets/luna

Amaranth HDL framework for monitoring, hacking, and developing USB devices

fpga hardware usb

Last synced: 02 Aug 2024

https://github.com/oneapi-src/oneAPI-samples

Samples for Intel® oneAPI Toolkits

ai cpu cuda fortran fpga gpu jupyter oneapi oneccl onedal onednn onedpl onemkl onetbb python pytorch rendering scikit-learn sycl tensorflow

Last synced: 31 Jul 2024

https://github.com/firesim/firesim

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

boom cloud datacenter firesim fpga hardware on-prem risc-v rocket-chip simulation

Last synced: 01 Aug 2024

https://github.com/riscvarchive/riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

asic fpga open-isa risc-v socs

Last synced: 02 Aug 2024

https://github.com/chipsalliance/Cores-VeeR-EH1

VeeR EH1 core

ahb-lite asic-design axi4 fpga fusesoc open-source-hardware processor risc risc-v riscv riscv32 rtl veer verilator western-digital

Last synced: 02 Aug 2024

https://github.com/ultraembedded/biriscv

32-bit Superscalar RISC-V CPU

artix-7 asic branch-prediction coremark cpu fpga in-order linux pipelined-processors risc-v riscv-linux rv32i rv32im superscalar verilator verilog xilinx

Last synced: 02 Aug 2024

https://github.com/FPGAwars/apio

:seedling: Open source ecosystem for open FPGA boards

apio cli fpga icestorm lattice manager package python verilog

Last synced: 02 Aug 2024

https://github.com/eugene-tarassov/vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

arty-a7 boom fpga genesys2 kc705 linux nexys-video risc-v riscv rocketchip vc707 vivado xilinx

Last synced: 02 Aug 2024

https://github.com/circuitvalley/USB_C_Industrial_Camera_FPGA_USB3

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

camera csi fpga mipi mipi-csi-receiver usb usb3 uvc verilog

Last synced: 01 Aug 2024

https://github.com/lnis-uofu/OpenFPGA

An Open-source FPGA IP Generator

fpga fpga-soc

Last synced: 30 Jul 2024

https://github.com/f4pga/prjxray

Documenting the Xilinx 7-series bit-stream format.

artix artix7 bitstream fpga fuzzer kintex7 symbiflow toolchain tools vivado xilinx xilinx-fpga

Last synced: 02 Aug 2024

https://github.com/romeric/Fastor

A lightweight high performance tensor algebra framework for modern C++

fpga hpc multidimensional-arrays simd small-blas tensor-contraction tensors

Last synced: 02 Aug 2024

https://github.com/VUnit/vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

asic fpga systemverilog-hdl testbench unit-testing universal-verification-methodology verification verilog-hdl vhdl

Last synced: 01 Aug 2024

https://github.com/Cr4sh/s6_pcie_microblaze

PCI Express DIY hacking toolkit for Xilinx SP605. This repository is also home of Hyper-V Backdoor and Boot Backdoor, check readme for links and info

backdoor dma fpga hyper-v hypervisor kernel microblaze pci-e rootkit uefi xilinx

Last synced: 01 Aug 2024

https://github.com/Xilinx/finn

Dataflow compiler for QNN inference on FPGAs

compiler dataflow fpga neural-network quantization

Last synced: 31 Jul 2024

https://github.com/xupsh/pp4fpgas-cn

中文版 Parallel Programming for FPGAs

fpga hls parallel-programming pynq

Last synced: 31 Jul 2024

https://github.com/fpgasystems/fpga-network-stack

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

100gbit fpga network roce tcp

Last synced: 02 Aug 2024

https://github.com/ultraembedded/cores

Various HDL (Verilog) IP Cores

asic audio fpga i2s rtl sdram spi sram uart usb verilator verilog verilog-components verilog-hdl

Last synced: 02 Aug 2024

https://github.com/m-labs/nmigen

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

fpga hdl nmigen yosys

Last synced: 02 Aug 2024

https://github.com/open-sdr/openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

ad9361 analog-devices csma dma fpga hardware hls ieee80211 linux mac80211 ofdm rtl sdr software-defined-radio verilog vhdl wi-fi xilinx zynq

Last synced: 01 Aug 2024

https://github.com/olofk/edalize

An abstraction library for interfacing EDA tools

altera eda fossi fpga ghdl icarus-verilog icestorm lattice modelsim riviera-pro simulation spyglass synthesis systemverilog verilator verilog vhdl vivado xilinx yosys

Last synced: 02 Aug 2024

https://github.com/nickg/nvc

VHDL compiler and simulator

compiler fpga simulator vhdl

Last synced: 30 Jul 2024

https://github.com/trivialmips/nontrivial-mips

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

cpu fpga fpga-soc fpga-soc-linux mips systemverilog xilinx

Last synced: 02 Aug 2024

https://github.com/xilinx/xrt

Run Time for AIE and FPGA based platforms

fpga linux-kernel vitis xrt

Last synced: 28 Sep 2024

https://github.com/projf/projf-explore

Project F brings FPGAs to life with exciting open-source designs you can build on.

fpga graphics-hardware oshw verilog

Last synced: 02 Aug 2024

https://github.com/JulianKemmerer/PipelineC

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

c fpga fpga-acceleration fpga-accelerators fpga-programming hardware hardware-description hardware-description-language high-level-synthesis hls open-source-hardware pipelines python vhdl

Last synced: 02 Aug 2024

https://github.com/Xilinx/XRT

Run Time for AIE and FPGA based platforms

fpga linux-kernel vitis xrt

Last synced: 02 Aug 2024

https://github.com/seldridge/verilog

Repository for basic (and not so basic) Verilog blocks with high re-use potential

fpga hardware rtl verilog

Last synced: 01 Oct 2024

https://github.com/VLSI-EDA/PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

altera asic fpga hardware-designs hardware-libraries hardware-modules lattice osvvm poc-library python regression-testing simulation synthesis testbenches uvvm verification vhdl vlsi vunit xilinx

Last synced: 02 Aug 2024

https://github.com/google/qkeras

QKeras: a quantization deep learning library for Tensorflow Keras

accelerator asic-design deep-learning fpga fpga-accelerator hardware-acceleration keras machine-learning quantization quantized-networks quantized-neural-networks tensorflow

Last synced: 31 Jul 2024

https://github.com/emsec/hal

HAL – The Hardware Analyzer

embedded-security fpga hal hardware integrated-circuits netlist reverse-engineering security

Last synced: 01 Aug 2024

https://github.com/WangXuan95/FPGA-USB-Device

An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。

cdc fpga keyboard rtl usb usb-audio usb-camera usb-cdc usb-controller usb-device usb-disk usb-hid usb-keyboard usb-microphone usb-serial usb-speaker usb-uart usb-uvc uvc verilog

Last synced: 02 Aug 2024

https://github.com/TerosTechnology/vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

fpga systemverilog verilog vhdl

Last synced: 02 Aug 2024

https://github.com/platformio/platformio-atom-ide

PlatformIO IDE for Atom: The next generation integrated development environment for IoT

arduino atom build debugger embedded esp32 esp8266 fpga hardware ide iot lattice libraries mbed microcontroller platformio verilog

Last synced: 27 Sep 2024

https://github.com/WangXuan95/BSV_Tutorial_cn

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

bluespec bluespec-systemverilog bsv fpga hardware-description-language hdl verilog

Last synced: 02 Aug 2024

https://github.com/spcl/dace

DaCe - Data Centric Parallel Programming

cuda fpga high-level-synthesis high-performance-computing programming-language vivado-hls

Last synced: 02 Aug 2024

https://github.com/jks-prv/Beagle_SDR_GPS

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

14-bit-adc beagle cape fpga gps hf open-source pcb sdr shortwave verilog vlf web-interface

Last synced: 01 Aug 2024

https://github.com/ZipCPU/wb2axip

Bus bridges and other odds and ends

axi-bus fpga gplv3 wishbone wishbone-bus xilinx xilinx-vivado

Last synced: 02 Aug 2024

https://github.com/vmware-archive/cascade

A Just-In-Time Compiler for Verilog from VMware Research

fpga hardware jit just-in-time repl verilog

Last synced: 02 Aug 2024

https://github.com/splinedrive/kianRiscV

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, linux soc included, .

cpu cyclone10lp divider ecp5 fpga ice40 ice40hx1k icebreaker icefun icoboard linux linuxsoc multiplier pipelined qmtech-board riscv rv32im softcpu ulx3s verilog

Last synced: 02 Aug 2024

https://github.com/f32c/f32c

A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz

altera arduino fpga lattice mips riscv xilinx

Last synced: 02 Aug 2024

https://github.com/rprinz08/hbpf

hBPF = eBPF in hardware

ebpf fpga litex migen python3

Last synced: 29 Sep 2024

https://github.com/jofrfu/tinytpu

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

assembly embedded-systems fpga fpga-accelerator hardware-acceleration hardware-architectures hardware-description-language hardware-designs internet-of-things iot ip-core linux tensor tensorflow tpu verilog vhdl vivado xilinx zynq

Last synced: 29 Sep 2024

https://github.com/tillitis/tillitis-key1

Board designs, FPGA verilog, firmware for TKey, the flexible and open USB security key 🔑

fpga open-hardware security-token

Last synced: 09 Aug 2024

https://github.com/circuitvalley/mipi_csi_receiver_FPGA

MIPI CSI-2 Camera Sensor Receiver verilog HDL implementation For any generic FPGA. Tested with IMX219 on Lattice MachXO3LF. 2Gbps UVC Video Stream Over USB 3.0 with Cypress FX3. This is now Legacy Version!

camera csi csi-2 cypress fpga fx3 lattice-fpga mipi mipi-csi-receiver usb3 uvc video