Projects in Awesome Lists tagged with gowin
A curated list of projects in awesome lists tagged with gowin .
https://github.com/trabucayre/openfpgaloader
Universal utility for programming FPGA
arty bitstream cyclone fpga gowin intel lattice trenz-gowin-littlebee xilinx
Last synced: 14 May 2025
https://github.com/trabucayre/openFPGALoader
Universal utility for programming FPGA
arty bitstream cyclone fpga gowin intel lattice trenz-gowin-littlebee xilinx
Last synced: 26 Mar 2025
https://github.com/vossstef/tang_nano_20k_c64
Commodore C64 core for the Tang Nano 20K Primer 25K Mega 60k and Mega 138K Pro FPGA
c64 commodore fpga gowin mist tang-nano tang-nano-20k tang-primer-25k
Last synced: 05 Mar 2025
https://github.com/harbaum/pacman-tangnano9k
A Pac-Man Arcade implementation for the TangNano9K using HDMI
arcade fpga gowin hdmi pacman tangnano9k verilog
Last synced: 05 Mar 2025
https://github.com/vossstef/vic20nano
Commodore VIC20 core for the Tang Nano 9k Nano 20k Primer 20k Primer 25k Mega 60k Mega138k Pro FPGA
commodore fpga gowin mist sipeed sipeed- sipeed-tang-138k-pro sipeed-tang-nano-20k sipeed-tang-nano-9k tang-nano tang-primer tang-primer-25k tangnano20k tangnano9k vic20
Last synced: 05 Mar 2025
https://github.com/lupyuen/gowin-blink
Blink demo for GOWIN FPGA dev kit DK-START-GW1N4
dk-start-gw1n4 fpga gowin gw1n-4
Last synced: 09 Oct 2025
https://github.com/itzzinfinity/100-days-of-rtl
Trying to get a new skill
altera digital electronics gowin modelsim quartus-prime rtl testbench verilog vivado xilinx xilinx-vivado
Last synced: 01 Nov 2025
https://github.com/sigma-logic/hdmi-14-tx
HDMI 1.4 Transmitter(Source) Core for GW5AST
fpga gowin hardware hardware-design hdl hdmi verilog
Last synced: 05 Apr 2025
https://github.com/hgszh/gowin_fpga_dds_spi_esp32_demo
FPGA-based DDS signal generation controlled by an ESP32 over SPI.
dac8830 dds esp32 gowin spi-slave tangnano9k
Last synced: 09 Oct 2025
https://github.com/sergz72/fpga
FPGA related stuff
assembler assembly-language bytecode-compiler cpu cyclone forth forth-cpu forth-language fpga fpga-programming gowin java java-cpu risc-v verilog
Last synced: 06 Jul 2025
https://github.com/sigma-logic/common-cores
Common cores for internal use under organization. Mostly oriented on Gowin Arora V family
fpga gowin hardware-design ip-core system-verilog verilog
Last synced: 26 Jul 2025
https://github.com/wojciechmarek/my-fpga-journey
A set of code examples for Tang Nano 1K FPGA board.
description-language fpga gowin hardware-description-language logic-circuit logic-gates synthesis tang-nano tang-nano-1k vhdl
Last synced: 07 Oct 2025
https://github.com/mcleber/verilog_traffic_light
First steps with the Sipeed Tang Primer 20k FPGA.
gowin gowin-eda learning-verilog sipeed sipeed-tang-primer verilog verilog-hdl
Last synced: 10 Mar 2025
https://github.com/mcleber/verilog_7-segment_display_with_dip_switches
This project implements a BCD (Binary-Coded Decimal) converter that reads DIP switch input and controls a 7-segment display, showing digits 0–8 or ‘E’ for invalid combinations.
gowin gowin-eda learning-verilog sipeed sipeed-tang-primer verilog verilog-hdl
Last synced: 03 Jul 2025
https://github.com/mcleber/verilog_studies
This repository contains my studies and experiments with Verilog HDL.
amd-xilinx gowin gowin-eda learning-verilog tang-primer-20k verilog verilog-hdl vivado vivado-vitis xilinx xilinx-fpga xilinx-vivado
Last synced: 10 Mar 2025