Projects in Awesome Lists tagged with hardware-description-language

https://github.com/clash-lang/clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

asic fpga hardware-description-language haskell systemverilog verilog vhdl

Last synced: 14 May 2025

https://github.com/juliankemmerer/pipelinec

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

c fpga fpga-acceleration fpga-accelerators fpga-programming hardware hardware-description hardware-description-language high-level-synthesis hls open-source-hardware pipelines python vhdl

Last synced: 15 May 2025

https://github.com/JulianKemmerer/PipelineC

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

c fpga fpga-acceleration fpga-accelerators fpga-programming hardware hardware-description hardware-description-language high-level-synthesis hls open-source-hardware pipelines python vhdl

Last synced: 22 Apr 2025

https://github.com/WangXuan95/BSV_Tutorial_cn

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

bluespec bluespec-systemverilog bsv fpga hardware-description-language hdl verilog

Last synced: 20 Apr 2025

https://github.com/jofrfu/tinytpu

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

assembly embedded-systems fpga fpga-accelerator hardware-acceleration hardware-architectures hardware-description-language hardware-designs internet-of-things iot ip-core linux tensor tensorflow tpu verilog vhdl vivado xilinx zynq

Last synced: 07 Apr 2025

https://github.com/SystemRDL/systemrdl-compiler

SystemRDL 2.0 language compiler front-end

asic csr design-automation eda fpga hardware-description-language register-description-language register-descriptions registers systemrdl systemrdl-compiler

Last synced: 11 May 2025

https://github.com/mit-plv/koika

A core language for rule-based hardware design 🦑

compilation coq formal-methods hardware-description-language programming-languages semantics

Last synced: 17 Jun 2025

https://github.com/mit-plv/kami

A Platform for High-Level Parametric Hardware Specification and its Modular Verification

bluespec coq hardware-description-language hardware-verification proof-assistant

Last synced: 08 Apr 2025

https://github.com/cyber-anubis/the-hack-general-purpose-computer

Using HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone computer hardware platform; Including Virtual machine,Compiler and Operating system.

arithmetic-logic-unit assembler compiler computer-architecture cpu hardware-description-language machine-language nand nand2tetris operating-system virtual-machine

Last synced: 14 May 2025

https://github.com/asyncvlsi/act

ACT hardware description language and core tools.

asynchronous-circuits asynchronous-vlsi cad chp circuit-simulator communicating-hardware-processes dataflow dataflow-programming design-automation eda hardware-description-language hdl language production-rules prs vlsi vlsi-cad

Last synced: 14 Mar 2025

https://github.com/SystemRDL/PeakRDL

Control and status register code generator toolchain

amba apb asic axi command-line-tool csr eda fpga hardware-description-language register-descriptions registers systemrdl-compiler systemverilog uvm uvm-register-model verilog

Last synced: 22 Apr 2025

https://github.com/pc2/sus-compiler

A new Hardware Design Language that keeps you in the driver's seat

fpga fpga-programming hardware-description-language hdl programming-language tree-sitter

Last synced: 04 Apr 2025

https://github.com/jeffdecola/my-verilog-examples

A place to keep my synthesizable verilog examples.

asic asic-design fpga gtkwave hardware hardware-architecture hardware-description-language hdl iverilog simulator synthesis synthesize systemverilog verilog verilog-simulator vivado waveform xilinx

Last synced: 20 Oct 2025

https://github.com/aofarmakis/nibbling-bits

Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.

assembler assembly computer-architecture computer-organization hardware-description-language instruction-set-architecture processor-design single-cycle-processor verilog

Last synced: 10 Apr 2025

https://github.com/drom/reqack

🔁 elastic circuit toolchain

hacktoberfest hardware-description-language hdl verilog

Last synced: 26 Apr 2025

https://github.com/chaseruskin/legoHDL

An experimental package manager and development tool for Hardware Description Languages (HDL).

digital-design digital-logic fpga hardware-description-language hardware-design hdl package-manager verilog vhdl

Last synced: 11 May 2025

https://github.com/chaseruskin/legohdl

An experimental package manager and development tool for Hardware Description Languages (HDL).

digital-design digital-logic fpga hardware-description-language hardware-design hdl package-manager verilog vhdl

Last synced: 11 Apr 2025

https://github.com/povik/fold

high abstraction synthesis

asic compiler fpga hardware-description-language high-level-synthesis

Last synced: 14 Apr 2025

https://github.com/gergoerdi/retroclash-lib

Library code for upcoming RetroClash book

clash fpga hardware-description-language keypad-matrix seven-segment-display uart-controller vga

Last synced: 19 Apr 2025

https://github.com/jpt13653903/alcha

A New Programming Language for FPGA Projects

fpga hardware-description-language programming-language

Last synced: 17 Jun 2025

https://github.com/david-palma/mips-32bit

Microprocessor without Interlocked Pipelined Stages (MIPS) architectures implemented in single-cycle and multi-cycle formats.

32-bit computer-architecture hardware-description-language hardware-designs instruction-set-architecture isa mips mips32 multi-cycle single-cycle vhdl

Last synced: 22 Oct 2025

https://github.com/meiniki/logip

Logic Analyzer IP Core

amd asic basys3 digital formal-verification fpga hardware-description-language hdl ip logicanalyzer logip measurements ols sump symbiyosys systemverilog verilog vivado xilinx

Last synced: 03 Jan 2026

https://github.com/choaib-elmadi/getting-started-with-verilog

Getting started with Verilog: Hardware Description Language for digital design.

circuit circuit-designing design digital hardware hardware-description-language hdl ics intel verilog verilog-hdl

Last synced: 28 Jul 2025

https://github.com/eforen/flowhs

Flow Based Hardware Simulator

computer-engineering flow-based-programming hardware-description-language hardware-designs hsl

Last synced: 06 Jul 2025

https://github.com/adolbyb/vhdl-fpga-nexys-a7

A collection of code from CDA 4240C: Design of Digital System and Lab

artix-7 fpga hardware-description-language hdl nexys-a7 verilog vhdl xilinx-vivado

Last synced: 16 Aug 2025

https://github.com/akhilrai28/single-port-ram

This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.

digital-circuits fpga fpga-programming hardware hardware-description-language memory-design ram single-port synchronous testbench verilog

Last synced: 15 Jul 2025

https://github.com/lironmiz/nand2tetriscourse

acadamic course in campus il about building a modern computer from basic logic gates such as "nand" to a general computer architecture that is designed execute any program such as "Tetris". and also building assambler

adders assembler assembly boolean-algebra boolean-arithmetic clock code-generation computer-architecture course cpu cycles flip-flops hardware-description-language learning-by-doing logic-gates machine-language memory-units parsing project register

Last synced: 02 Apr 2025

https://github.com/engineeringsoftware/hdlp

Code and data for "On the Naturalness of Hardware Descriptions" in ESEC/FSE'20

deep-learning hardware-description-language machine-learning naturalness pytorch systemverilog verilog vhdl

Last synced: 12 May 2025

https://github.com/azazhassankhan/vhdlcodecraft

Welcome to the "VHDL_Coding_Designs" repository, your gateway to the world of VHDL (VHSIC Hardware Description Language) and digital design. This is the space where hardware meets innovation, and digital concepts come to life. 🌐

designs dld hardware-description-language vhdl-code vivado

Last synced: 15 Mar 2025

https://github.com/azazhassankhan/fpga_building_blocks_vhdl

Welcome to the "VHDL_Coding_Designs" repository, your gateway to the world of VHDL (VHSIC Hardware Description Language) and digital design. This is the space where hardware meets innovation, and digital concepts come to life. 🌐

designs dld hardware-description-language vhdl-code vivado

Last synced: 02 Jul 2025