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Projects in Awesome Lists tagged with verilog-hdl

A curated list of projects in awesome lists tagged with verilog-hdl .

https://github.com/VUnit/vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

asic fpga systemverilog-hdl testbench unit-testing universal-verification-methodology verification verilog-hdl vhdl

Last synced: 18 Apr 2025

https://github.com/PyHDI/Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

code-generator compiler control-flow-analyzer dataflow-analyzer hardware parser python verilog-hdl

Last synced: 18 Apr 2025

https://github.com/sudhamshu091/32-Verilog-Mini-Projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

miniproject verilog verilog-hdl verilog-project

Last synced: 14 Mar 2025

https://github.com/NNgen/nngen

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

compiler deep-learning hardware high-level-synthesis neural-network onnx python pyverilog verilog-hdl veriloggen

Last synced: 22 Apr 2025

https://github.com/PyHDI/veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

compiler hardware hardware-construction-language high-level-synthesis python pyverilog verilog-hdl

Last synced: 15 Mar 2025

https://github.com/dpretet/async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asic asic-design async cdc cross-clock-domain fifo fifo-cache fifo-queue fpga hdl icarus-verilog synthesis verification verilator verilog verilog-hdl

Last synced: 22 Apr 2025

https://github.com/ultraembedded/core_jpeg

High throughput JPEG decoder in Verilog for FPGA

axi-stream fpga jpeg-decoder mjpeg motion-jpeg verilog verilog-hdl

Last synced: 01 Mar 2025

https://github.com/tvlad1234/fakepga

Simulating Verilog designs on a microcontroller

fpga pico-sdk rp2040 simulator verilator verilog verilog-hdl

Last synced: 18 Feb 2025

https://github.com/AUCOHL/Fault

A complete open-source design-for-testing (DFT) Solution

atpg dft eda fault-simulation jtag scan-chains stuck-at testing verilog verilog-hdl vlsi-cad

Last synced: 22 Apr 2025

https://github.com/ben-marshall/uart

A simple implementation of a UART modem in Verilog.

fpga hardware uart uart-verilog verilog verilog-hdl

Last synced: 28 Oct 2025

https://github.com/michaelehab/aes-verilog

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

aes aes-128 aes-192 aes-256 aes-decryption aes-encryption cryptography encryption encryption-decryption fpga fpga-board fpga-soc learn rtl security verilog verilog-hdl verilog-project

Last synced: 01 Aug 2025

https://github.com/michaelvll/riscv_cpu

A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

risc-v verilog-hdl

Last synced: 24 Oct 2025

https://github.com/thesupercd/8bit_microcomputer_verilog

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

8bit ben-eater ben-eaters-cpu iverilog verilog verilog-code verilog-hdl verilog-project

Last synced: 05 Apr 2025

https://github.com/defparam/higan-verilog

This is a higan/Verilator co-simulation example/framework

emulation emulator fpga simulation snes snes-programming verilog verilog-hdl

Last synced: 09 Apr 2025

https://github.com/chili-chips-ba/openxc7-tetrisaraj

Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.

basys3 fpga gamedev nextpnr open-source rtl soc tetris-game verilog-hdl xc7a35t xilinx yosys

Last synced: 31 Mar 2025

https://github.com/yasnakateb/pipelinedarm

💎 A 32-bit ARM Processor Implementation in Verilog HDL

arm arm-pipeline arm-processor cpu icarus-verilog iverilog verilog verilog-hdl

Last synced: 13 Mar 2025

https://github.com/jn513/risco-5

Multi-cycle RISC-V processor with RV32I/E[M] implementation, built during a few days off.

arquitetura fpga risc-v riscv riscv32 verilog verilog-hdl

Last synced: 02 Apr 2025

https://github.com/cla7aye15i4nd/trivial-riscv-cpu

A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA with at 100MHz.

computer-architecture fpga pipeline riscv tomasulo-algorithm verilog-hdl

Last synced: 12 Mar 2025

https://github.com/LSC-Unicamp/processor_ci

Utility scripts to configure processors, perform synthesis, load onto FPGAs, and other tasks related to ProcessorCI.

ci-cd cicd eda hardware risc-v riscv verilog verilog-hdl

Last synced: 21 Sep 2025

https://github.com/lsc-unicamp/processor_ci

Utility scripts to configure processors, perform synthesis, load onto FPGAs, and other tasks related to ProcessorCI.

ci-cd cicd eda hardware risc-v riscv verilog verilog-hdl

Last synced: 01 Sep 2025

https://github.com/mshr-h/motion_estimation_processor_fullsearch

Fullsearch based Motion Estimation Processor written in Verilog-HDL

motion-estimation verilog-hdl video-codec video-processing

Last synced: 04 Oct 2025

https://github.com/yasnakateb/nocrouter

👶🏻 My first baby steps into the world of NoC

icarus-verilog iverilog router verilog verilog-hdl

Last synced: 13 Jul 2025

https://github.com/nishit0072e/rtl-to-gdsii

Complete installation flow of yosys, OpenSTA and OpenROAD for RTL Verification, Synthesis, Timing Analysis, Power Analysis & GDSII layout generation

gds2 openroad power time verilog-hdl yosys

Last synced: 06 Sep 2025

https://github.com/yasnakateb/pipelinedmips

🔮 A 16-bit MIPS Processor Implementation in Verilog HDL

cpu icarus-verilog iverilog mips mips-pipeline mips-processor pipeline verilog verilog-hdl

Last synced: 11 Oct 2025

https://github.com/teddy-van-jerry/arm_lite

A lite version of ARM CPU that extends ARM LEGv8

arm armv8 cpu forwarding pipeline verilog verilog-hdl

Last synced: 25 Mar 2025

https://github.com/sysprog21/vga-nyancat

Hardware-accelerated Nyancat animation on VGA display, implemented in Verilog RTL

nyancat verilator verilog-hdl

Last synced: 28 Oct 2025

https://github.com/addisonelliott/logifindfpgatest

This is a Quartus Prime FPGA project testing the functionality of the LogiFind Altera Cyclone IV EP4CE6E22C8N Development Board. This product can also be found on eBay where I bought it from. I hope to provide base code that will help others in their learning with this development board.

7-segment altera buzzer cyclone-iv easyfpga ep4ce6e22c8n fpga ir-receiver logifind nec-verilog pl2303 quartus-prime uart-verilog verilog verilog-hdl

Last synced: 28 Mar 2025

https://github.com/luk3sky/building-a-processor---project

Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic

alu hdl processor-architecture verilog-hdl verilog-project

Last synced: 21 Mar 2025

https://github.com/jn513/grande-risco-5

Processador RISC-V multi ciclo com implementação RV32IMBC_Zicsr construído em alguns dias de folga.

arquitetura fpga risc-v riscv riscv32 verilog verilog-hdl

Last synced: 02 Apr 2025

https://github.com/jn513/pequeno-risco-5

Processador RISC-V de ciclo único com implementação RV32I construído em alguns dias de folga.

arquitetura risc-v riscv riscv32 verilog verilog-hdl

Last synced: 09 Aug 2025

https://github.com/malaksadek/statictiminganalyzer

A Logic Circuit Static Timing Analyzer Implemented in Python 🔌 ⚡ (2018)

c graph-algorithms html json logic-circuit logic-gates python scl static-timing-analysis verilog verilog-hdl

Last synced: 23 Apr 2025

https://github.com/zhijian-liu/mips-cpu

A toy CPU with five-stage MIPS pipeline

mips-instructions pipeline-cpu verilog-hdl

Last synced: 06 Apr 2025

https://github.com/choaib-elmadi/getting-started-with-verilog

Getting started with Verilog: Hardware Description Language for digital design.

circuit circuit-designing design digital hardware hardware-description-language hdl ics intel verilog verilog-hdl

Last synced: 28 Jul 2025

https://github.com/pvgupta24/von-neumann-architecture-cpu

Implementation of 8-Bit CPU based on Von-Neumann Architechture in HDL

cpu cpu-simulator verilog verilog-hdl von-neumann

Last synced: 18 Oct 2025

https://github.com/nellyw8/verireason

This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation

ai4eda code-generation eda hardware hdl large-language-models llama llm openr1 qwen reasoning reasoning-language-models reinforcement-learning research-paper rlhf testbench-generator-verilog verilog verilog-code verilog-hdl verilogeval

Last synced: 20 Jun 2025

https://github.com/vadman97/picosim

Xilinx Picoblaze Assembly Simulator and Debugger

assembly picoblaze picoblaze-assembly picoblaze-devices simulation verilog-hdl xilinx

Last synced: 13 Apr 2025

https://github.com/shyamal-anadkat/wisc-sp13

CS 552 term project : functional design of a microprocessor called the WISC-SP13

cs552 hardware-designs mips-assembly processor processor-architecture verilog verilog-hdl

Last synced: 15 Aug 2025

https://github.com/mshr-h/fibonacci_verilog

fibonacci number calculator written in Verilog-HDL

altera fibonacci fibonacci-numbers iverilog verilog-hdl

Last synced: 25 Jun 2025

https://github.com/kyori19/verilog-otp

VerilogHDL implementation of One-Time Password Algorithm (HOTP)

hotp onetimepassword systemverilog verilog verilog-hdl

Last synced: 05 Jul 2025

https://github.com/1c3t3a/canny-zybo-z7

Implementation of a Canny-Edge Detector on a Zybo-Z7 FPGA.

canny-edge-detection fpga-programming verilog-hdl

Last synced: 05 Apr 2025

https://github.com/yasnakateb/aes

🔐 Hardware Implementation Of AES Algorithm in Verilog HDL

aes aes-128 aes-encryption encryption encryption-algorithm icarus-verilog iverilog verilog verilog-hdl

Last synced: 13 Mar 2025

https://github.com/1sand0s/ssp-master-and-slave-verilog-module

FSM based SPI/SSP Master and Slave Verilog Module

fifo-buffer rtl verilog verilog-hdl

Last synced: 02 Apr 2025

https://github.com/shuai132/dma_axis_ltc2324_16

LTC2324-16 driver for Xilinx AXI-DMA

adi axi-dma ltc2324 verilog-hdl

Last synced: 09 Apr 2025

https://github.com/nikhilrout/verilog-dsd

Verilog implementations of fundamental combinational and sequential circuits (with testbenches)

verilog verilog-hdl

Last synced: 13 Apr 2025

https://github.com/anjanasenanayake/verilog-model-for-8bit-processor

An implementation of a processor with basic components coded in verilog

alu computer-architecture digital-design opcode processor register verilog verilog-hdl

Last synced: 21 Jun 2025

https://github.com/aniketsingh03/cachememory

This project is an implementation of cache memory with load and store instructions in Verilog.

c cache-memory verilog-hdl

Last synced: 06 Apr 2025

https://github.com/yashbhutwala/mips-cpu

Implementation of a MIPS CPU in Verilog from CSCI 320: Computer Architecture

computer-architecture cpu mips verilog-hdl

Last synced: 14 May 2025

https://github.com/vowstar/qsoc

QSoC - Quick System on Chip Studio

soc verilog-hdl

Last synced: 28 Apr 2025

https://github.com/samiyaalizaidi/direct-digital-synthesizer

Direct Digital Synthesizer for Generating Sine Waves using Verilog HDL

digital-system-design direct-digital-synthesizer sine-wave-generator verilog-code verilog-hdl

Last synced: 06 Mar 2025

https://github.com/mshr-h/motion_estimation_processor_4pixsearch

4-pix search based Motion Estimation Processor written in Verilog-HDL

motion-estimation verilog-hdl video-codec video-processing

Last synced: 02 Apr 2025

https://github.com/mshr-h/motion_estimation_processor_breakingoff

Breakingoff based Motion Estimation Processor written in Verilog-HDL

motion-estimation verilog-hdl video-codec video-processing

Last synced: 10 Oct 2025

https://github.com/muhammadtalhasami/sv_verilator

System verilog learning journey. Here in this repo you learn about how to write system verilog test bench using verilator tool a c++ test bench. Verilator is basically a 2 state tool .

system-verilog-testbench systemverilog testbench verification verilator- verilator-testbench verilog verilog-hdl

Last synced: 08 Apr 2025

https://github.com/jn513/baby-risco-5

Multi-cycle RISC-V processor with RV32E implementation

riscv riscv32 riscv32e verilog verilog-hdl

Last synced: 02 Apr 2025

https://github.com/jn513/estudos_verilog

Exemplos feito em verilog para estudos

fpga fpga-programming hardware verilog verilog-code verilog-hdl

Last synced: 02 Apr 2025

https://github.com/mummanajagadeesh/i2c-protocol-verilog

Verilog Implementation of I2C Protocol using Finite State Machine (FSM) design

finite-state-machine fpga fsm i2c i2cprotocol verilog verilog-hdl verilog-project xilinx xilinx-vivado

Last synced: 20 Mar 2025

https://github.com/abdallahabusidu/CMP305-introduction-Verilog

introduction to Verilog in Integrated Circuit Design And VLSI technology

verilog verilog-code verilog-hdl verilog-project

Last synced: 11 Aug 2025

https://github.com/pavlostzitzos/hdls-intro

SystemVerilog , Verilog , Verilog-A , Verilog-AMS tutorial

verilog verilog-hdl verilog-testbenches vhdl

Last synced: 08 Aug 2025

https://github.com/shinowtf/fgpa-rfid-door-access-gate-control-with-de2-115

This is my University Digital System Assignment which using Verilog HDLCode to code DE2-115 board for RFID access card door control

digital-system-design rfid rtldesign verilog-hdl

Last synced: 17 Aug 2025

https://github.com/samiyaalizaidi/fifo-in-verilog

Implementation of a FIFO structure for Digital Systems | Written in Verilog HDL

digital-system-design fifo-buffer fifo-queue verilog-hdl vivado

Last synced: 06 Mar 2025

https://github.com/jn513/fpga_basics

Basic FPGA demo circuits made in Verilog HDL, VHDL and SystemVerilog

basic fpga learning verilog verilog-hdl vhdl vhdl-code

Last synced: 26 Feb 2025

https://github.com/kitune-san/kfmmc_v2

Multi media card access controller written in HDL

hdl mmc multimediacard sdc sdcard verilog verilog-hdl

Last synced: 15 Mar 2025

https://github.com/abdallahabusidu/cmp305-introduction-verilog

introduction to Verilog in Integrated Circuit Design And VLSI technology

verilog verilog-code verilog-hdl verilog-project

Last synced: 31 Mar 2025

https://github.com/tmahlburg/mriscv

simple, modular rv32i implementation (WIP)

risc-v riscv riscv32 rv32i verilog verilog-hdl

Last synced: 10 Mar 2025

https://github.com/galihru/logicsim

The Logic Simulator is an advanced tool designed to facilitate the understanding of sequential circuit design. This application implements fundamental concepts of computer architecture and digital systems engineering through an intuitive drag-and-drop interface, providin

logic-gates logic-simulator pwa-apps verilog-hdl verilog-project verilog-simulator

Last synced: 11 Oct 2025

https://github.com/mshr-h/verilog_building_block

Verilog building blocks with high chance of re-use

verilog-hdl

Last synced: 25 Oct 2025

https://github.com/rdsik/schoolriscv

CPU microarchitecture, step by step

assembly makefile modelsim quartus verilog-hdl

Last synced: 04 Oct 2025

https://github.com/mcleber/verilog_exercises

This repository contains my studies and experiments on Verilog HDL.

amd-xilinx learning-verilog verilog verilog-hdl vivado vivado-vitis xilinx xilinx-fpga xilinx-vivado

Last synced: 05 Sep 2025

https://github.com/kenny2github/verilog-cpu

A very rudimentary and haphazard CPU created in Verilog.

cpu verilog verilog-hdl

Last synced: 30 Oct 2025

https://github.com/mthszr/stopwatch

Projeto para a disciplina IF675 de Sistemas Digitais no CIn-UFPE, no qual consiste em desenvolver um cronômetro digital, utilizando Verilog com a base de Máquina de Estados Finitos.

verilog verilog-hdl

Last synced: 16 Mar 2025

https://github.com/gcerpa01/compe470

Work of my projects I worked on while enrolled in SDSU's COMPE470 Digital Circuits course in Spring 2023

verilog verilog-hdl vivado

Last synced: 06 Mar 2025

https://github.com/skpro-glitch/resume

Find my resume, encapsulating my most prominent projects and experiences relevant for an entry level Hardware Engineering role. - Soham Kapur

algorithms-and-data-structures cadence cadence-virtuoso drone electronics-engineering java java-programming ltspice matlab soham-kapur sohamkapur team-aviators-international uav verilog verilog-hdl verilog-processor vit-chennai vit-university vitc vitchennai

Last synced: 27 Oct 2025

https://github.com/theveryhim/fft-display-using-zynq7000

Signal processing using Zynq7000 Board(AX7010)

c matlab signal-processing verilog-hdl

Last synced: 03 Jul 2025

https://github.com/mcleber/verilog_7-segment_display_with_dip_switches

This project implements a BCD (Binary-Coded Decimal) converter that reads DIP switch input and controls a 7-segment display, showing digits 0–8 or ‘E’ for invalid combinations.

gowin gowin-eda learning-verilog sipeed sipeed-tang-primer verilog verilog-hdl

Last synced: 03 Jul 2025

https://github.com/mcleber/verilog_traffic_light

First steps with the Sipeed Tang Primer 20k FPGA.

gowin gowin-eda learning-verilog sipeed sipeed-tang-primer verilog verilog-hdl

Last synced: 10 Mar 2025

https://github.com/peplxx/keyboard-driver-vhdl

Driver for handling matrix keyboard 4x4 on FPGA Board

driver fpga fpga-programming hardware keyboard verilog verilog-hdl

Last synced: 06 Apr 2025