Projects in Awesome Lists tagged with fulladder
A curated list of projects in awesome lists tagged with fulladder .
https://github.com/mahdizynali/verilog-digital-circuit-codes
simple verilog digital circuits sampels (halfAdder, fullAdder, ALSU , ...)
arithmatic fulladder fullsubtractor halfadder halfsubtractor logic multiplexer mux shift-left shift-register shift-right verilog verilog-code
Last synced: 28 Feb 2026
https://github.com/helias/circuitsimulator
A project that simulate the circuits FullAdder and FullSubtractor
fulladder university university-project web-app web-application
Last synced: 31 Jan 2026
https://github.com/anjanasenanayake/verilog-model-for-4bit-alu
4 bit ALU in verilog
4bit alu computer-architecture fulladder latch verilog verilog-hdl
Last synced: 15 Feb 2026
https://github.com/meysam81/full-adder-3-bit
from back in the university, a digital design laboratory project adding 2 number of 3 bits
3-bit adder full-adder fulladder proteus
Last synced: 02 Jan 2026
https://github.com/barannmeisterr/32-bit-alu-design
This project is a 32-bit Arithmetic Logic Unit (ALU) designed in SystemVerilog as part of a MIPS microprocessor simulation. The ALU supports various arithmetic and logical operations and includes a custom-built 32-bit full adder, one 2-to-1 MUX, one 4-to-1 MUX, one AND gate , one OR gate and the Zero Extend Logic
alu arithmetic-logic-unit computerorganization fulladder inverter logic-gates multiplexer mux systemverilog verilog
Last synced: 13 Feb 2026
