Projects in Awesome Lists tagged with verilog-code

https://github.com/thesupercd/8bit_microcomputer_verilog

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

8bit ben-eater ben-eaters-cpu iverilog verilog verilog-code verilog-hdl verilog-project

Last synced: 05 Apr 2025

https://github.com/benitoss/unamiga

Implementation of Amiga 500/1200 in Altera Cyclone IV FPGA

verilog-code

Last synced: 13 Apr 2025

https://github.com/geraked/verilog-rle

Verilog Implementation of Run Length Encoding for RGB Image Compression

compression-algorithm computer-engineering fpga fpga-programming geraked image-compression image-processing ise matlab rabist rle rle-compression-algorithm run-length-encoding student-project verilog verilog-code verilog-hdl xilinx xilinx-fpga yazd-university

Last synced: 06 May 2025

https://github.com/aditeyabaral/ddco-lab-ue18cs207

A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.

computer-organization digital-design icarus-verilog logic-programming verilog verilog-code

Last synced: 09 Mar 2025

https://github.com/mahdizynali/verilog-digital-circuit-codes

simple verilog digital circuits sampels (halfAdder, fullAdder, ALSU , ...)

arithmatic fulladder fullsubtractor halfadder halfsubtractor logic multiplexer mux shift-left shift-register shift-right verilog verilog-code

Last synced: 25 Feb 2025

https://github.com/nellyw8/verireason

This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation

ai4eda code-generation eda hardware hdl large-language-models llama llm openr1 qwen reasoning reasoning-language-models reinforcement-learning research-paper rlhf testbench-generator-verilog verilog verilog-code verilog-hdl verilogeval

Last synced: 20 Jun 2025

https://github.com/samiyaalizaidi/direct-digital-synthesizer

Direct Digital Synthesizer for Generating Sine Waves using Verilog HDL

digital-system-design direct-digital-synthesizer sine-wave-generator verilog-code verilog-hdl

Last synced: 06 Mar 2025

https://github.com/ehsanshahbazii/digital-vlsi-system-design-projects

سورس کد پروژه های درس طراحی سیستم های دیجیتال برنامه پذیر دانشگاه تبریز مقطع کارشناسی رشته مهندسی کامپیوتر

verilog verilog-code verilog-components verilog-project vlsi

Last synced: 24 Apr 2025

https://github.com/abdallahabusidu/cmp305-introduction-verilog

introduction to Verilog in Integrated Circuit Design And VLSI technology

verilog verilog-code verilog-hdl verilog-project

Last synced: 31 Mar 2025

https://github.com/chrnthnkmutt/carpark_verilog

This project is using for illustrating on making the circuit on Xillin's BASYS3 from AMD and Verilog Language on Vivado, on the scope of car parking system

basys3 basys3-fpga fpga verilog verilog-code verilog-project

Last synced: 04 Mar 2025

https://github.com/abdallahabusedo/cmp305-introduction-verilog

introduction to Verilog in Integrated Circuit Design And VLSI technology

verilog verilog-code verilog-hdl verilog-project

Last synced: 13 Dec 2024

https://github.com/melchisedech333/verilog-experiments

:space_invader: My studies with Verilog and notions of digital systems.

digital-system-design digital-systems digital-systems-design digital-systems-fundamentals hdl icarus-verilog verilog verilog-code verilog-examples verilog-hdl verilog-project

Last synced: 29 Mar 2025

https://github.com/jn513/estudos_verilog

Exemplos feito em verilog para estudos

fpga fpga-programming hardware verilog verilog-code verilog-hdl

Last synced: 02 Apr 2025

https://github.com/camilaqpereira/oficina-verilog-siecomp

Neste repositório estão disponibilizados todos os arquivos utilizados na Oficina Introdução ao Verilog Comportamental ministrado na XXXI SIECOMP (UEFS). Além disso, estão listados múltiplos recursos para estudo da linguagem.

oficina verilog verilog-code verilog-hdl

Last synced: 17 Mar 2025

https://github.com/hmarchiori/controle-microondas-verilog

Este projeto em Verilog implementa dois módulos principais para controle de um timer, componente de um sistema de microondas. O microondas contém uma máquina de estados finitas, controle lógico para ativação, pausa, e finalização, bem como controle de potência, ativada por meio de controles físicos.

digital-design fpga hdl microwave seven-segment seven-segments-display verilog verilog-code