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Projects in Awesome Lists tagged with verilog-project

A curated list of projects in awesome lists tagged with verilog-project .

https://github.com/sudhamshu091/32-Verilog-Mini-Projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

miniproject verilog verilog-hdl verilog-project

Last synced: 14 Mar 2025

https://github.com/thesupercd/8bit_microcomputer_verilog

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

8bit ben-eater ben-eaters-cpu iverilog verilog verilog-code verilog-hdl verilog-project

Last synced: 05 Apr 2025

https://github.com/ultraembedded/minispartan6-audio

miniSpartan6+ (Spartan6) FPGA based MP3 Player

audio fpga mp3player risc-v rv32im sd-card spartan6 verilog verilog-project

Last synced: 01 Mar 2025

https://github.com/michaelehab/aes-verilog

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

aes aes-128 aes-192 aes-256 aes-decryption aes-encryption cryptography encryption encryption-decryption fpga fpga-board fpga-soc learn rtl security verilog verilog-hdl verilog-project

Last synced: 04 Mar 2025

https://github.com/pescetti-studio/flipga01

FPGA (Verilog) implementation of the Flip01 8-bit processor.

8-bit 8-bit-computer 8-bit-cpu 8bit cpu flip01 fpga verilog verilog-project

Last synced: 15 Mar 2025

https://github.com/cw1997/sdram-controller

SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol

hardware hardware-designs sdram sdram-controller systemverilog verilog-project

Last synced: 22 Mar 2025

https://github.com/rismicrodevices/rmr8pm3001a

Taurus 3001 RISC-V 64-bit Privileged Minimal System Processor for T110/T28 ASIC

jasse out-of-order risc-v rv64 rv64i verilator verilog verilog-project ysyx3 ysyx4

Last synced: 14 Apr 2025

https://github.com/luk3sky/building-a-processor---project

Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic

alu hdl processor-architecture verilog-hdl verilog-project

Last synced: 21 Mar 2025

https://github.com/cw1997/graphical_card

a graphical card for displaying text on VGA text mode by D-Sub port

graphical-programming hardware hardware-designs systemverilog-simulation verilog verilog-project

Last synced: 22 Mar 2025

https://github.com/aditeyabaral/up-down-counter

A simple up-down counter made using icarus verilog as a part of the Digital Design and Computer Organization course (UE18CS201) at PES University.

counter digital-design icarus-verilog logic-programming verilog verilog-project

Last synced: 09 Mar 2025

https://github.com/dopebiscuit/ieee-digital-ic-design

This repo is for my IEEE ASU Student Branch Digital IC Design workshop, an introduction to digital design using Verilog, this is a documentation of my tasks.

digital-design-and-computer-organization logic-design verilog-project

Last synced: 31 Mar 2025

https://github.com/ehsanshahbazii/digital-vlsi-system-design-projects

سورس کد پروژه های درس طراحی سیستم های دیجیتال برنامه پذیر دانشگاه تبریز مقطع کارشناسی رشته مهندسی کامپیوتر

verilog verilog-code verilog-components verilog-project vlsi

Last synced: 24 Apr 2025

https://github.com/chrnthnkmutt/carpark_verilog

This project is using for illustrating on making the circuit on Xillin's BASYS3 from AMD and Verilog Language on Vivado, on the scope of car parking system

basys3 basys3-fpga fpga verilog verilog-code verilog-project

Last synced: 04 Mar 2025

https://github.com/abdallahabusedo/cmp305-introduction-verilog

introduction to Verilog in Integrated Circuit Design And VLSI technology

verilog verilog-code verilog-hdl verilog-project

Last synced: 13 Dec 2024

https://github.com/abdallahabusidu/cmp305-introduction-verilog

introduction to Verilog in Integrated Circuit Design And VLSI technology

verilog verilog-code verilog-hdl verilog-project

Last synced: 31 Mar 2025

https://github.com/jjateen/snake-game-verilog

This repository showcases a Verilog-based Snake and Apple Game, developed for the ECL 106: Digital System Design with HDL course. Running on an Altera DE10-Lite FPGA board and displayed on a VGA monitor, players control a snake to collect apples while avoiding obstacles. The snake grows longer with each apple, making the game progressively harder.

altera-fpga de10-lite fpga quartus-prime verilog verilog-project

Last synced: 10 Mar 2025

https://github.com/erickmari/proyecto-digitales-ii

Diseño de un par controlador-periférico según el protocolo MDIO (cláusula 22)

iverilog mdio verilog-project

Last synced: 26 Mar 2025

https://github.com/mummanajagadeesh/i2c-protocol-verilog

Verilog Implementation of I2C Protocol using Finite State Machine (FSM) design

finite-state-machine fpga fsm i2c i2cprotocol verilog verilog-hdl verilog-project xilinx xilinx-vivado

Last synced: 20 Mar 2025

https://github.com/princeranjan03/imageencryption_i-chip

This project focuses on creating a hardware-based encryption and decryption system that implements the Data Encryption Standard (DES) algorithm.

cipher cryptography data-encryption data-encryption-standard encoding encryption-decryption fpga image image-processing opencv rtldesign source-coding verilog verilog-hdl verilog-project vivado xilinx xilinx-vivado

Last synced: 26 Mar 2025

https://github.com/tahirzia-1/uart-transmitter-and-receiver

A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.

fpga-board fpga-programming fpga-soc nexys4ddr rtl simulation systemverilog testbench uart uart-receiver uart-transmitter uart-verilog verilog verilog-hdl verilog-project vivado vivado-hls vivado-simulator

Last synced: 04 Mar 2025