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Projects in Awesome Lists tagged with hdl
A curated list of projects in awesome lists tagged with hdl .
https://github.com/amaranth-lang/amaranth
A modern hardware definition language and toolchain based on Python
Last synced: 17 Dec 2024
https://github.com/langhuihui/monibuca
🧩 Monibuca is a Modularized, Extensible framework for building Streaming Server
flv hdl hls livestream mediaserver rtmp rtp rtsp ts webrtc websocket
Last synced: 19 Dec 2024
https://github.com/analogdevicesinc/hdl
HDL libraries and projects
analog-devices fpga hacktoberfest hdl jesd204b verilog
Last synced: 04 Dec 2024
https://github.com/aappleby/metroboy
A repository of gate-level simulators and tools for the original Game Boy.
emulator gameboy gameboy-emulator hdl simulator verilog
Last synced: 20 Dec 2024
https://github.com/m-labs/nmigen
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
Last synced: 21 Dec 2024
https://github.com/WangXuan95/BSV_Tutorial_cn
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
bluespec bluespec-systemverilog bsv fpga hardware-description-language hdl verilog
Last synced: 09 Nov 2024
https://github.com/Nuand/bladeRF-wiphy
bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
80211 bladerf dsss hdl ofdm ofdm-wireless-communications rtl vhdl
Last synced: 29 Oct 2024
https://github.com/intel/rohd
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
framework hardware hardware-design hardware-verification hdl rtl simulator verification
Last synced: 26 Oct 2024
https://github.com/pymtl/pymtl3
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
cycle-level-modeling hardware-generation hdl multi-level-modeling open-source-eda open-source-hardware pymtl python rtl systemverilog verilog
Last synced: 09 Nov 2024
https://github.com/tensil-ai/tensil
Open source machine learning accelerators
artificial-intelligence asic fpga hdl machine-learning scala silicon
Last synced: 09 Nov 2024
https://github.com/analogdevicesinc/plutosdr-fw
PlutoSDR Firmware
active-learning-module adalm-pluto fpga hdl iio linux plutosdr plutosdr-firmware plutosdr-fw rf sdr transceiver
Last synced: 21 Dec 2024
https://github.com/kitware/veloview
VeloView performs real-time visualization and easy processing of live captured 3D LiDAR data from Velodyne sensors (Alpha Prime™, Puck™, Ultra Puck™, Puck Hi-Res™, Alpha Puck™, Puck LITE™, HDL-32, HDL-64E). Runs on Windows, Linux and MacOS. This repository is a mirror of https://gitlab.kitware.com/LidarView/VeloView-Velodyne.
hdl lidar lidar-camera-calibration lidar-data-manipulation lidar-measurements sensor-data sensor-streaming velodyne velodyne-hdl-sensors velodyne-sensor
Last synced: 16 Dec 2024
https://github.com/Kitware/VeloView
VeloView performs real-time visualization and easy processing of live captured 3D LiDAR data from Velodyne sensors (Alpha Prime™, Puck™, Ultra Puck™, Puck Hi-Res™, Alpha Puck™, Puck LITE™, HDL-32, HDL-64E). Runs on Windows, Linux and MacOS. This repository is a mirror of https://gitlab.kitware.com/LidarView/VeloView-Velodyne.
hdl lidar lidar-camera-calibration lidar-data-manipulation lidar-measurements sensor-data sensor-streaming velodyne velodyne-hdl-sensors velodyne-sensor
Last synced: 14 Nov 2024
https://github.com/spamegg1/reviews
Reviewing some online CS courses I took
algorithms assembly c computer-graphics databases hdl java javascript kotlin logic mathematics nand2tetris networking operating-systems programming-languages python racket ruby scala smlnj
Last synced: 20 Dec 2024
https://github.com/chipsalliance/sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
compliance-testing hdl rtl symbiflow systemverilog verilog
Last synced: 05 Nov 2024
https://github.com/f4pga/f4pga-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
architecture-definitions artix artix7 documentation fpga hdl ice40 kintex7 lattice primitives python sphinx symbiflow synthesis toolchain verilog verilog-simulations verilog-simulator vpr xilinx-fpga
Last synced: 09 Nov 2024
https://github.com/dpretet/async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
asic asic-design async cdc cross-clock-domain fifo fifo-cache fifo-queue fpga hdl icarus-verilog synthesis verification verilator verilog verilog-hdl
Last synced: 10 Nov 2024
https://github.com/catkira/open5g_phy
A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog
5g 5g-nr 5g-simulation fpga hdl verilog
Last synced: 19 Dec 2024
https://github.com/masc-ucsc/livehd
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
asic fpga hdl lgraph live simulation synthesis
Last synced: 25 Oct 2024
https://github.com/kactus2/kactus2dev
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
design eda fpga hardware hdl ip-xact mpsoc reuse system-on-chip
Last synced: 09 Nov 2024
https://github.com/1801BM1/cpu11
Revengineered ancient PDP-11 CPUs, originals and clones
cpucore engineering hdl pdp-11 retrocomputing reverse verilog
Last synced: 30 Nov 2024
https://github.com/aappleby/metron
A C++ to Verilog translation tool with some basic guarantees that your code will work.
c compiler cpp fpga hdl transpiler verilog
Last synced: 19 Dec 2024
https://github.com/bogdanvuk/pygears
HW Design: A Functional Approach
asic design fpga functional hardware hdl python simulator
Last synced: 17 Nov 2024
https://github.com/asyncvlsi/act
ACT hardware description language and core tools.
asynchronous-circuits asynchronous-vlsi cad chp circuit-simulator communicating-hardware-processes dataflow dataflow-programming design-automation eda hardware-description-language hdl language production-rules prs vlsi vlsi-cad
Last synced: 25 Oct 2024
https://github.com/WilsonChen003/HDLGen
HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
asic automation hdl perl python rtl script soc verilog
Last synced: 26 Oct 2024
https://github.com/DFiantHDL/DFiant
DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
asic dataflow dataflow-programming fpga hdl
Last synced: 09 Nov 2024
https://github.com/DFiantHDL/DFHDL
DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
asic dataflow dataflow-programming fpga hdl
Last synced: 17 Nov 2024
https://github.com/pc2/sus-compiler
A new Hardware Design Language that keeps you in the driver's seat
fpga fpga-programming hardware-description-language hdl programming-language tree-sitter
Last synced: 18 Dec 2024
https://github.com/trcwm/speech256
An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.
fpga hdl retrochallenge speech synthesizer verilog
Last synced: 06 Nov 2024
https://github.com/SymbiFlow/sphinxcontrib-hdl-diagrams
Sphinx Extension which generates various types of diagrams from Verilog code.
diagrams documentation documentation-tool fpga hdl rtl sphinx sphinx-extension symbiflow verilog yosys
Last synced: 17 Nov 2024
https://github.com/analogdevicesinc/m2k-fw
M2k firmware for the ADALM-2000 Active Learning Module
active-learning-module adalm-2000 fpga hdl iio linux logic-analyzer m2k network-analyzer oscilloscope signal-generation spectrum-analyzer
Last synced: 09 Nov 2024
https://github.com/sam210723/fpga
Collection of projects for various FPGA development boards
5a-75b colorlight fpga hdl icestudio icesugar icesugar-nano mimas-v2 tinyfpga tinyfpga-bx verilog vga vga-driver
Last synced: 16 Nov 2024
https://github.com/paebbels/picoblaze-library
The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).
assembler fpga hardware hardware-architectures hardware-designs hardware-libraries hdl picoblaze-devices picoblaze-library poc-library simulation soc synthesis verilog vhdl
Last synced: 08 Nov 2024
https://github.com/jiegec/fpu-wrappers
Wrappers for open source FPU hardware implementations.
Last synced: 14 Dec 2024
https://github.com/jeffdecola/my-verilog-examples
A place to keep my synthesizable verilog examples.
asic asic-design fpga gtkwave hardware hardware-architecture hardware-description-language hdl iverilog simulator synthesis synthesize systemverilog verilog verilog-simulator vivado waveform xilinx
Last synced: 10 Dec 2024
https://github.com/drom/reqack
🔁 elastic circuit toolchain
hacktoberfest hardware-description-language hdl verilog
Last synced: 02 Nov 2024
https://github.com/IBM/perfect-chisel
Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program
Last synced: 09 Nov 2024
https://github.com/hukenovs/tcl_for_fpga
TCL scripts for FPGA (Xilinx)
clock-groups fpga hdl synth tcl tcl-scripts vivado xilinx
Last synced: 19 Nov 2024
https://github.com/m-labs/nmigen-boards
Board and connector definition files for nMigen
Last synced: 09 Nov 2024
https://github.com/shehanmunasinghe/tinygpu
tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog
computer-organization gpu hdl processor-design simd systemverilog
Last synced: 18 Dec 2024
https://github.com/buhe/bugu-computer
💻 Build own computer by fpga.
fpga hdl nand2tetris own tutorials verilog
Last synced: 13 Dec 2024
https://github.com/bensampson5/libsv
An open source, parameterized SystemVerilog digital hardware IP library
asic asic-library digital-design fpga fpga-library hardware hardware-designs hardware-libraries hdl ip systemverilog verilog
Last synced: 17 Nov 2024
https://github.com/chaseruskin/orbit
An agile package manager and extensible build tool for HDLs
agile agile-development build-tool command-line-tool cross-platform hardware hdl package-manager systemverilog verilog vhdl
Last synced: 14 Nov 2024
https://github.com/SymbiFlow/sphinx-verilog-domain
Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
hdl rtl sphinx sphinx-domain sphinx-extension systemverilog verilog verilog-library
Last synced: 17 Nov 2024
https://github.com/myriadrf/freesrp_gw
The FPGA design for the FreeSRP's Artix 7 FPGA
Last synced: 07 Nov 2024
https://github.com/analogdevicesinc/highspeedconvertertoolbox
MATLAB toolbox for ADI high speed converter products
ad9081 hacktoberfest hdl hdl-coder matlab
Last synced: 09 Nov 2024
https://github.com/chaseruskin/legohdl
An experimental package manager and development tool for Hardware Description Languages (HDL).
digital-design digital-logic fpga hardware-description-language hardware-design hdl package-manager verilog vhdl
Last synced: 14 Nov 2024
https://github.com/chaseruskin/legoHDL
An experimental package manager and development tool for Hardware Description Languages (HDL).
digital-design digital-logic fpga hardware-description-language hardware-design hdl package-manager verilog vhdl
Last synced: 17 Nov 2024
https://github.com/nverno/nand-hdl-mode
Emacs major mode for editing NAND hardware description language files (.hdl)
Last synced: 17 Nov 2024
https://github.com/nhynes/chisel3-axi
Chisel3 AXI4-{Lite, Full, Stream} Definitions
Last synced: 11 Oct 2024
https://github.com/lethalbit/discretize
A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad
electronics hdl verilog yosys-plugin
Last synced: 06 Nov 2024
https://github.com/mattvenn/frequency_counter
Project 2.2 Frequency counter
Last synced: 15 Dec 2024
https://github.com/catkira/cic
HDL code for a complex multiplier with AXI stream interface
Last synced: 01 Nov 2024
https://github.com/clarkfieseln/fpga_hw_sim_fwk_2
FPGA Hardware Simulation Framework
api emulation emulator fpga fpga-programming hdl pygubu pygubu-designer python python-3 python3 simulation simulator vhdl vhdl-code windows windows-10 windows-11 windows10
Last synced: 10 Nov 2024
https://github.com/jiegec/espinallib
Reusable small hardware components for SpinalHDL
Last synced: 09 Nov 2024
https://github.com/jc-ll/ruby_rtl
Describing RTL circuit in Ruby
digital-circuits dsl hdl migen vhdl
Last synced: 15 Dec 2024
https://github.com/raleighlittles/applied_digital_logic_exercises_using_fpgas
Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.
applied-digital-logic-exercises artix-7 basys3 fpga hdl microblaze-mcs verilog vivado
Last synced: 28 Nov 2024
https://github.com/mattvenn/wrapped_rgb_mixer
Demo project for the Zero to ASIC Course.
Last synced: 15 Dec 2024
https://github.com/trcwm/fptool
Compiler for generating fixed-point logic using VHDL
arithmetic fixed-point hdl signal-processing vhdl
Last synced: 06 Nov 2024
https://github.com/donn/phi
Hardware description language that tries not to suck
compilers eda fpga hdl phi systemverilog verilog
Last synced: 28 Nov 2024
https://github.com/danielvieiravega/vcdparser
Value Change Dump (VCD) File
hdl simulations value-change-dump vcd verilog vhdl
Last synced: 15 Nov 2024
https://github.com/catkira/complex_multiplier
HDL code for a complex multiplier with AXI stream Interface
Last synced: 01 Nov 2024
https://github.com/catkira/dds
HDL code for a DDS (direct digital synthesizer) with AXI stream interface
Last synced: 01 Nov 2024
https://github.com/luk3sky/building-a-processor---project
Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic
alu hdl processor-architecture verilog-hdl verilog-project
Last synced: 27 Nov 2024
https://github.com/izyasoft/easyhdllib
A coocbook of HDL (primarily Verilog) modules
altera clock-divider fifo fpga frequencies frequency-analysis hdl verilog verilog-components verilog-hdl verilog-library verilog-snippets xilinx-fpga
Last synced: 20 Dec 2024
https://github.com/choaib-elmadi/getting-started-with-vhdl
Getting started with VHDL: Very High Speed Integrated Circuit Hardware Description Language.
fpga fpga-programming hdl vhdl vhdl-code vhdl-examples
Last synced: 22 Nov 2024
https://github.com/wokwi/hdl-parser
Parser for nand2tetris HDL (Hardware Description Language), written in JavaScript
Last synced: 16 Nov 2024
https://github.com/vanditg/comp-sci-7081---computer-systems
This repository contains assignments, quizzes, workshops, and practical exam solutions for one of my postgraduate subjects of COMP SCI 7081 - Computer Systems. The programming language will be HDL.
computer-systems hdl token tokenization tokenizer
Last synced: 05 Nov 2024
https://github.com/dcbuild3r/nand2tetris
Solving through nand2tetris.org challenges
Last synced: 17 Dec 2024
https://github.com/raleighlittles/basys3countdownclock
Extremely basic countdown clock project for the Basys 3 FPGA development board.
basys-3 basys3 fpga hdl seven-segment-display verilog vivado xdc xilinx
Last synced: 28 Nov 2024
https://github.com/nkyorov/logic-gates-hdl
Implementations of various logic gates in HDL
Last synced: 17 Nov 2024
https://github.com/javacafe01/bitcoin-hash
A reimplementation of the Bitcoin hash, both in parallel and serial
bitcoin hashing hdl systemverilog
Last synced: 02 Nov 2024
https://github.com/416rehman/computer-from-scratch
A project aimed at building a modern computer bottom-up from scratch
32-bit chip chipset circuit hardware hdl logic-gates nand2tetris
Last synced: 17 Nov 2024
https://github.com/jeffdecola/my-masters-thesis
A High-Level Design Framework Illustrating Technology Migration.
fpga hdl masters-degree masters-thesis technology-migration thesis vhdl
Last synced: 13 Dec 2024
https://github.com/shyamal-anadkat/the-11-of-us
adc ece551 flight-controller hdl integrator quadcopter synthesis system-verilog uart verilog vhdl
Last synced: 16 Dec 2024
https://github.com/melchisedech333/verilog-experiments
:space_invader: My studies with Verilog and notions of digital systems.
digital-system-design digital-systems digital-systems-design digital-systems-fundamentals hdl icarus-verilog verilog verilog-code verilog-examples verilog-hdl verilog-project
Last synced: 08 Dec 2024
https://github.com/kkinos/ktc32
A hobby 32-bit CPU implemented in SystemVerilog.
Last synced: 18 Dec 2024
https://github.com/yezzfusl/flexcomswitch
VHDL controller for dynamic protocol switching (CAN, LIN, FlexRay).
canprotocol communicationcontroller digitaldesign embeddedsystems engineering flexray fpga hardwaredesign hardwareengineering hdl linprotocol simulation vhdl
Last synced: 14 Nov 2024
https://github.com/mluby/logic-gates
A Hardware Description Language for logic gates interpreted by js
cpu hardware-description-language hdl
Last synced: 07 Nov 2024
https://github.com/icarogabryel/flooat
Hardware description language, simulator and python module. It is designed to be friendly, simple, light and productive. More easy to use and learn than Verilog and VHDL.
computer-architecture computer-organization digital-circuits eletronics hardware-description-language hardware-designs hdl integrated-circuits processor-architecture python python-module simulation
Last synced: 17 Nov 2024
https://github.com/susiejojo/sobel_filter
Sobel filter for edge detection in images supporting parallel processing using Verilog on Xilinx ISE 13.4
hdl sobel-filter verilog xilinx-ise
Last synced: 17 Dec 2024
https://github.com/davoodeh/verilog2hspice
Do some simple conversions on Verilog files to make them compatible with HSpice
Last synced: 15 Dec 2024
