Projects in Awesome Lists tagged with hdl

https://github.com/amaranth-lang/amaranth

A modern hardware definition language and toolchain based on Python

amaranth-hdl fpga hdl

Last synced: 30 Sep 2024

https://github.com/analogdevicesinc/hdl

HDL libraries and projects

analog-devices fpga hacktoberfest hdl jesd204b verilog

Last synced: 30 Sep 2024

https://github.com/langhuihui/monibuca

🧩 Monibuca is a Modularized, Extensible framework for building Streaming Server

flv hdl hls livestream mediaserver rtmp rtp rtsp ts webrtc websocket

Last synced: 30 Sep 2024

https://github.com/aappleby/metroboy

A repository of gate-level simulators and tools for the original Game Boy.

emulator gameboy gameboy-emulator hdl simulator verilog

Last synced: 30 Sep 2024

https://github.com/m-labs/nmigen

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

fpga hdl nmigen yosys

Last synced: 02 Aug 2024

https://github.com/WangXuan95/BSV_Tutorial_cn

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

bluespec bluespec-systemverilog bsv fpga hardware-description-language hdl verilog

Last synced: 02 Aug 2024

https://github.com/Nuand/bladeRF-wiphy

bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

80211 bladerf dsss hdl ofdm ofdm-wireless-communications rtl vhdl

Last synced: 31 Jul 2024

https://github.com/intel/rohd

The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

framework hardware hardware-design hardware-verification hdl rtl simulator verification

Last synced: 30 Jul 2024

https://github.com/pymtl/pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

cycle-level-modeling hardware-generation hdl multi-level-modeling open-source-eda open-source-hardware pymtl python rtl systemverilog verilog

Last synced: 02 Aug 2024

https://github.com/tensil-ai/tensil

Open source machine learning accelerators

artificial-intelligence asic fpga hdl machine-learning scala silicon

Last synced: 02 Aug 2024

https://github.com/analogdevicesinc/plutosdr-fw

PlutoSDR Firmware

active-learning-module adalm-pluto fpga hdl iio linux plutosdr plutosdr-firmware plutosdr-fw rf sdr transceiver

Last synced: 26 Sep 2024

https://github.com/Kitware/VeloView

VeloView performs real-time visualization and easy processing of live captured 3D LiDAR data from Velodyne sensors (Alpha Prime™, Puck™, Ultra Puck™, Puck Hi-Res™, Alpha Puck™, Puck LITE™, HDL-32, HDL-64E). Runs on Windows, Linux and MacOS. This repository is a mirror of https://gitlab.kitware.com/LidarView/VeloView-Velodyne.

hdl lidar lidar-camera-calibration lidar-data-manipulation lidar-measurements sensor-data sensor-streaming velodyne velodyne-hdl-sensors velodyne-sensor

Last synced: 03 Aug 2024

https://github.com/slaclab/surf

A huge VHDL library for FPGA development

asic firmware fpga hdl python vhdl

Last synced: 02 Aug 2024

https://github.com/spamegg1/reviews

Reviewing some online CS courses I took

algorithms assembly c computer-graphics databases hdl java javascript kotlin logic mathematics nand2tetris networking operating-systems programming-languages python racket ruby scala smlnj

Last synced: 01 Oct 2024

https://github.com/chipsalliance/sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

compliance-testing hdl rtl symbiflow systemverilog verilog

Last synced: 02 Aug 2024

https://github.com/f4pga/f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

architecture-definitions artix artix7 documentation fpga hdl ice40 kintex7 lattice primitives python sphinx symbiflow synthesis toolchain verilog verilog-simulations verilog-simulator vpr xilinx-fpga

Last synced: 02 Aug 2024

https://github.com/dpretet/async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asic asic-design async cdc cross-clock-domain fifo fifo-cache fifo-queue fpga hdl icarus-verilog synthesis verification verilator verilog verilog-hdl

Last synced: 02 Aug 2024

https://github.com/masc-ucsc/livehd

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

asic fpga hdl lgraph live simulation synthesis

Last synced: 30 Jul 2024

https://github.com/yupferris/kaze

An HDL embedded in Rust.

digital-logic-design hdl rust

Last synced: 30 Jul 2024

https://github.com/kactus2/kactus2dev

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

design eda fpga hardware hdl ip-xact mpsoc reuse system-on-chip

Last synced: 02 Aug 2024

https://github.com/kevinpt/symbolator

HDL symbol generator

hdl symbol verilog vhdl

Last synced: 03 Aug 2024

https://github.com/1801BM1/cpu11

Revengineered ancient PDP-11 CPUs, originals and clones

cpucore engineering hdl pdp-11 retrocomputing reverse verilog

Last synced: 09 Aug 2024

https://github.com/bogdanvuk/pygears

HW Design: A Functional Approach

asic design fpga functional hardware hdl python simulator

Last synced: 03 Aug 2024

https://github.com/asyncvlsi/act

ACT hardware description language and core tools.

asynchronous-circuits asynchronous-vlsi cad chp circuit-simulator communicating-hardware-processes dataflow dataflow-programming design-automation eda hardware-description-language hdl language production-rules prs vlsi vlsi-cad

Last synced: 30 Jul 2024

https://github.com/DFiantHDL/DFHDL

DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language

asic dataflow dataflow-programming fpga hdl

Last synced: 03 Aug 2024

https://github.com/WilsonChen003/HDLGen

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

asic automation hdl perl python rtl script soc verilog

Last synced: 30 Jul 2024

https://github.com/davidthings/hdelk

Web-based HDL diagramming tool

browser diagrams edges elkjs fpga graphs hdelk hdl javascript nodes

Last synced: 03 Aug 2024

https://github.com/SymbiFlow/sphinxcontrib-hdl-diagrams

Sphinx Extension which generates various types of diagrams from Verilog code.

diagrams documentation documentation-tool fpga hdl rtl sphinx sphinx-extension symbiflow verilog yosys

Last synced: 03 Aug 2024

https://github.com/tymonx/virtio

Virtio implementation in SystemVerilog

cmake fpga hdl model quartus rtl systemc systemverilog verilator verilog virtio vivado xilinx

Last synced: 02 Aug 2024

https://github.com/paebbels/picoblaze-library

The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).

assembler fpga hardware hardware-architectures hardware-designs hardware-libraries hdl picoblaze-devices picoblaze-library poc-library simulation soc synthesis verilog vhdl