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Projects in Awesome Lists tagged with risc-v

A curated list of projects in awesome lists tagged with risc-v .

https://github.com/mytechnotalent/reverse-engineering

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

arm arm-assembly assembly assembly-language assembly-language-programming c c-plus-plus cyber-security cybersecurity go golang hacking malware reverse-engineering reverse-engineering-tutorial risc-v riscv rust x64 x86

Last synced: 17 Dec 2024

https://github.com/rt-thread/rt-thread

RT-Thread is an open source IoT Real-Time Operating System (RTOS).

aiot arm cortex-a cortex-m embedded-systems iot kernel microcontroller microkernel mips real-time risc-v rtos

Last synced: 16 Dec 2024

https://github.com/RT-Thread/rt-thread

RT-Thread is an open source IoT real-time operating system (RTOS).

aiot arm cortex-a cortex-m embedded-systems iot kernel microcontroller microkernel mips real-time risc-v rtos

Last synced: 27 Oct 2024

https://github.com/tock/tock

A secure embedded operating system for microcontrollers

arm cortex-m embedded iot kernel mcu microcontroller operating-system risc-v rust secure-operating-system tock

Last synced: 16 Dec 2024

https://github.com/michaing/dietpi

Lightweight justice for your single-board computer!

bash debian dietpi lightweight nanopi odroid optimization pine64 raspberrypi risc-v sbc shell

Last synced: 17 Dec 2024

https://github.com/MichaIng/DietPi

Lightweight justice for your single-board computer!

bash debian dietpi lightweight nanopi odroid optimization pine64 raspberrypi risc-v sbc shell

Last synced: 31 Oct 2024

https://github.com/openxiangshan/xiangshan

Open-source high-performance RISC-V processor

chisel microarchitecture risc-v

Last synced: 17 Dec 2024

https://github.com/alibaba/alios-things

面向IoT领域的、高可伸缩的物联网操作系统，可去官网了解更多信息https://www.aliyun.com/product/aliosthings

embedded haas haas-python iot microcontroller os risc-v rtos

Last synced: 18 Dec 2024

https://github.com/alibaba/AliOS-Things

面向IoT领域的、高可伸缩的物联网操作系统，可去官网了解更多信息https://www.aliyun.com/product/aliosthings

embedded haas haas-python iot microcontroller os risc-v rtos

Last synced: 07 Nov 2024

https://github.com/OpenXiangShan/XiangShan

Open-source high-performance RISC-V processor

chisel microarchitecture risc-v

Last synced: 25 Oct 2024

https://github.com/chyyuu/os_kernel_lab

OS kernel labs based on Rust/C Lang & RISC-V 64/X86-32

kernel lab os risc-v rust

Last synced: 19 Dec 2024

https://github.com/misprit7/computerraria

A fully compliant RISC-V computer made inside the game Terraria

logic-gates risc-v riscv terraria terraria-mod

Last synced: 18 Dec 2024

https://github.com/k2-fsa/sherpa-onnx

Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 servers, websocket server/client, C/C++, Python, Kotlin, C#, Go, NodeJS, Java, Swift, Dart, JavaScript, Flutter, Object Pascal, Lazarus, Rust

aarch64 android arm32 asr cpp csharp dotnet ios lazarus linux macos mfc object-pascal onnx raspberry-pi risc-v speech-to-text text-to-speech vits windows

Last synced: 16 Dec 2024

https://github.com/mortbopet/ripes

A graphical processor simulator and assembly editor for the RISC-V ISA

computer-architecture cpu-emulator education processor-architecture qt risc risc-v simulator

Last synced: 18 Dec 2024

https://github.com/SI-RISCV/e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

china core cpu nuclei risc-v ultra-low-power verilog

Last synced: 10 Nov 2024

https://github.com/mortbopet/Ripes

A graphical processor simulator and assembly editor for the RISC-V ISA

computer-architecture cpu-emulator education processor-architecture qt risc risc-v simulator

Last synced: 29 Oct 2024

https://github.com/openhwgroup/cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

ariane asic cpu fpga risc-v rv64gc systemverilog-hdl

Last synced: 19 Dec 2024

https://github.com/darklife/darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

core cpu fpga processor processor-design risc-v riscv rtl rv32e rv32i softcore verilog

Last synced: 05 Dec 2024

https://github.com/limine-bootloader/limine

Modern, advanced, portable, multiprotocol bootloader and boot manager.

aarch64 arm arm64 bios boot-loader boot-manager bootloader efi gpt loongarch loongarch64 loongson mbr risc-v riscv riscv64 uefi x64 x86 x86-64

Last synced: 19 Dec 2024

https://github.com/gem5/gem5

The official repository for the gem5 computer-system architecture simulator.

architecture arm modeling open-source risc-v simulation simulator x86

Last synced: 17 Dec 2024

https://github.com/rcore-os/rcore-tutorial-v3

Let's write an OS which can run on RISC-V in Rust from scratch!

k210 operating-system rcore risc-v rust

Last synced: 19 Dec 2024

https://github.com/risc0/risc0

RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.

cryptography risc-v rust stark virtual-machine zero-knowledge

Last synced: 16 Dec 2024

https://github.com/rcore-os/rCore-Tutorial-v3

Let's write an OS which can run on RISC-V in Rust from scratch!

k210 operating-system rcore risc-v rust

Last synced: 29 Oct 2024

https://github.com/ucb-bar/chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

accelerators boom chip-generator chipyard chisel firesim hwacha out-of-order peripherals risc-v riscv rocket rocket-chip rtl soc superscalar

Last synced: 18 Dec 2024

https://github.com/renode/renode

Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems

arm embedded-systems iot renode risc-v simulation x86

Last synced: 04 Dec 2024

https://github.com/olofk/serv

SERV - The SErial RISC-V CPU

asic fpga risc-v verilog

Last synced: 04 Dec 2024

https://github.com/stnolting/neorv32

:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

asic asip cpu embedded fpga gdb microcontroller neorv32 openocd processor risc-v riscv rtl rv32 safety soc soft-core system-on-chip verilog vhdl

Last synced: 27 Oct 2024

https://github.com/lowrisc/ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

cpucore hardware risc-v rv32

Last synced: 19 Nov 2024

https://github.com/lowRISC/ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

cpucore hardware risc-v rv32

Last synced: 27 Oct 2024

https://github.com/rcore-os/rcore-tutorial-book-v3

A book about how to write OS kernels in Rust easily.

k210 operating-system rcore risc-v rust

Last synced: 19 Dec 2024

https://github.com/thethirdone/rars

RARS -- RISC-V Assembler and Runtime Simulator

assembler education ide mars risc-v riscv simulator

Last synced: 19 Dec 2024

https://github.com/rcore-os/rCore-Tutorial-Book-v3

A book about how to write OS kernels in Rust easily.

k210 operating-system rcore risc-v rust

Last synced: 06 Nov 2024

https://github.com/simdutf/simdutf

Unicode routines (UTF8, UTF16, UTF32) and Base64: billions of characters per second using SSE2, AVX2, NEON, AVX-512, RISC-V Vector Extension, LoongArch64. Part of Node.js, WebKit/Safari, Ladybird, Chromium, Cloudflare Workers and Bun.

avx-512 avx2 base64 neon risc-v simd sse2 transcoding unicode utf16 utf8

Last synced: 19 Dec 2024

https://github.com/TheThirdOne/rars

RARS -- RISC-V Assembler and Runtime Simulator

assembler education ide mars risc-v riscv simulator

Last synced: 29 Oct 2024

https://github.com/sysprog21/shecc

A self-hosting and educational C optimizing compiler

arm armv7 c compiler compiler-optimization cross-compiler elf linux qemu risc-v riscv rv32i rv32im self-hosting ssa-form

Last synced: 20 Dec 2024

https://github.com/eugene-tarassov/vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

arty-a7 boom fpga genesys2 kc705 linux nexys-video risc-v riscv rocketchip vc707 vivado xilinx

Last synced: 10 Nov 2024

https://github.com/riscvarchive/riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

asic fpga open-isa risc-v socs

Last synced: 09 Nov 2024

https://github.com/firesim/firesim

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

boom cloud datacenter firesim fpga hardware on-prem risc-v rocket-chip simulation

Last synced: 01 Nov 2024

https://github.com/syntacore/scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

core ip risc-v riscv rtl rv32e rv32emc rv32i rv32imc verilog

Last synced: 29 Oct 2024

https://github.com/pimaker/rvc

A 32-bit RISC-V emulator in a shader (and C)

hlsl risc-v shader unity vrchat

Last synced: 21 Dec 2024

https://github.com/PiMaker/rvc

A 32-bit RISC-V emulator in a shader (and C)

hlsl risc-v shader unity vrchat

Last synced: 21 Nov 2024

https://github.com/Wren6991/Hazard3

3-stage RV32IMACZb* processor with debug

jtag risc-v riscv

Last synced: 07 Dec 2024

https://github.com/takahirox/riscv-rust

RISC-V processor emulator written in Rust+WASM

cpu emulator processor risc-v riscv rust wasm webassembly

Last synced: 15 Dec 2024

https://github.com/fnuecke/oc2

RISC-V VMs in Minecraft.

java minecraft mod risc-v vm

Last synced: 20 Dec 2024

https://github.com/lazyparser/weloveinterns

PLCT Lab ❤️ Interns!

interns internship risc-v

Last synced: 13 Nov 2024

https://github.com/wren6991/hazard3

3-stage RV32IMACZb* processor with debug

jtag risc-v riscv

Last synced: 12 Nov 2024

https://github.com/eclipse-embed-cdt/eclipse-plugins

The Eclipse Embedded CDT plug-ins for Arm & RISC-V C/C++ developers (formerly known as the GNU MCU Eclipse plug-ins). Includes the archive of previous plug-ins versions, as Releases.

arm cdt eclipse eclipse-marketplace embedded plug-ins plugins risc-v

Last synced: 15 Nov 2024

https://github.com/mikeroyal/risc-v-guide

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

android-app computer-architecture cpu-profiling hypervisor optimize peripherals platformio processor processor-architecture risc-processor risc-v riscv riscv-emulator riscv64 rv32 sbc sel4 simulator tensoflow-lite virtualization

Last synced: 21 Dec 2024

https://github.com/mikeroyal/RISC-V-Guide

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

android-app computer-architecture cpu-profiling hypervisor optimize peripherals platformio processor processor-architecture risc-processor risc-v riscv riscv-emulator riscv64 rv32 sbc sel4 simulator tensoflow-lite virtualization

Last synced: 25 Oct 2024

https://github.com/cvut/qtrvsim

RISC-V CPU simulator for education purposes

computer-architecture cpu-emulator risc-v teaching

Last synced: 21 Dec 2024

https://github.com/riscvarchive/riscv-software-list

The RISC-V software tools list, as seen on riscv.org

open-source risc-v

Last synced: 25 Oct 2024

https://github.com/openhwgroup/core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

risc-v systemverilog uvm verification

Last synced: 20 Dec 2024

https://github.com/larsbrinkhoff/lbforth

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

6502 8051 arm asmjs avr compiler cortex-m forth interpreter linux m68k metacompiler msp430 pdp11 programming-language risc-v riscv self-hosted x86

Last synced: 21 Dec 2024

https://github.com/sdima1357/esp32_usb_soft_host

ESP32 software USB host through general IO pins. We can connect up to 4 USB-LS HID (keyboard mouse joystick) devices simultaneously.

board emulators esp32 esp32c3 espressif iot retrocomputing retrogaming risc-v usb usb-hid usb-host xtensa

Last synced: 16 Dec 2024

https://github.com/larsbrinkhoff/lbForth

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

6502 8051 arm asmjs avr compiler cortex-m forth interpreter linux m68k metacompiler msp430 pdp11 programming-language risc-v riscv self-hosted x86

Last synced: 09 Nov 2024

https://github.com/t-k-233/risc-v-single-cycle-cpu

RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel

chisel logisim risc-v verilog

Last synced: 19 Dec 2024

https://github.com/MicroCoreLabs/Projects

Ted Fried's MicroCore Labs Projects which include microsequencer-based FPGA cores and emulators for the 8088, 8086, 8051, 6502, 68000, Z80, Risc-V, and also Typewriter and EPROM Emulator projects. MCL51, MCL64, MCL65, MCL65+, MCL68, MCL86, MCL86+, MCL86jr, MCLR5, MCLZ8, MCL6809

6502 68000 6809 8051 8051-microcontroller 8086 8088 apple2 atari2600 commodore-64 commodore64 eprom-emulator intel-8086 motorola-68000 nabu pcjr pcxt risc-v z80 z80-emulator

Last synced: 20 Nov 2024

https://github.com/riscv/meta-riscv

OpenEmbedded/Yocto layer for RISC-V Architecture

openembedded openembedded-layer risc-v riscv yocto yocto-layer yocto-meta

Last synced: 29 Nov 2024

https://github.com/WangXuan95/USTC-RVSoC

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

cpu fpga risc-v riscv rtl rv32i soc softcore systemverilog verilog

Last synced: 09 Nov 2024

https://github.com/beehive-lab/maxine-vm

Maxine VM: A meta-circular research VM

aarch64 armv7 c1x graal java jvm maxine-vm metacircular-vm research risc-v riscv t1x x86

Last synced: 15 Dec 2024

https://github.com/emproof-com/nyxstone

Nyxstone: assembly / disassembly library based on LLVM, implemented in C++ with Rust and Python bindings, maintained by emproof.com

aarch64 arm assembly disassembly infosec mips powerpc reverse-engineering risc-v security thumb x86 x86-64

Last synced: 13 Dec 2024

https://github.com/grahamedgecombe/icicle

32-bit RISC-V system on chip for iCE40 FPGAs

fpga ice40 icestorm risc-v

Last synced: 17 Dec 2024

https://github.com/skyzh/core-os-riscv

🖥️ An xv6-like operating system on RISC-V with multi-core support. Documentation available online.

cargo operating-system qemu risc-v rust xv6

Last synced: 20 Dec 2024

https://github.com/roalogic/RV12

RISC-V CPU Core

32-bit 64bit cpu risc-v

Last synced: 19 Nov 2024

https://github.com/Ko-oK-OS/xv6-rust

🦀️ Re-implement xv6-riscv in Rust

risc-v rust xv6-riscv

Last synced: 09 Nov 2024

https://github.com/ataraxialinux/ataraxia

Simple and lightweight source-based multi-platform Linux distribution with musl libc.

arm compact cross-compiler cross-platform distribution fast linux linux-distribution mips musl musl-libc powerpc privacy risc-v safe simple x86

Last synced: 18 Dec 2024

https://github.com/mrlsd/riscv-fs

F# RISC-V Instruction Set formal specification

cpu fs fsharp isa library risc-processor risc-v riscv riscv-emulator riscv-simulator riscv32 riscv64

Last synced: 18 Dec 2024

https://github.com/mrLSD/riscv-fs

F# RISC-V Instruction Set formal specification

cpu fs fsharp isa library risc-processor risc-v riscv riscv-emulator riscv-simulator riscv32 riscv64

Last synced: 09 Nov 2024

https://github.com/RoaLogic/RV12

RISC-V CPU Core

32-bit 64bit cpu risc-v

Last synced: 09 Nov 2024

https://github.com/pulp-platform/mempool

A 256-RISC-V-core system with low-latency access into shared L1 memory.

asic manycore risc-v

Last synced: 09 Nov 2024

https://github.com/ultraembedded/fpgamp

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

artix-7 fpga fpga-media-player hd-video hdmi ir-codes jpeg-decoder mjpeg motion-jpeg risc-v rtos sd-card vga

Last synced: 18 Dec 2024

https://github.com/wren6991/riscboy

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

cpu fpga gameboy pcb risc risc-v

Last synced: 18 Dec 2024

https://github.com/sysprog21/semu

A minimalist RISC-V system emulator capable of running Linux kernel

emulator linux-kernel risc-v riscv riscv-emulator rv32ima

Last synced: 15 Dec 2024

https://github.com/tvlad1234/pico-rv32ima

Running Linux on RP2040 with the help of RISC-V emulation

buildroot linux risc-v riscv-emulator riscv32 rp2040

Last synced: 18 Dec 2024

https://github.com/IsaacWoods/poplar

Microkernel and userspace written in Rust exploring modern ideas

kernel microkernel operating-system os osdev risc-v rust x86-64

Last synced: 09 Nov 2024

https://github.com/isaacwoods/poplar

Microkernel and userspace written in Rust exploring modern ideas

kernel microkernel operating-system os osdev risc-v rust x86-64

Last synced: 21 Dec 2024

https://github.com/patryk27/kartoffels

a game where you're given a potato and your job is to implement a firmware for it

fighting-game game mmo real-time risc-v riscv robot rust simulation

Last synced: 21 Dec 2024

https://github.com/standardsemiconductor/lion

Where Lions Roam: RISC-V on the VELDT

clash haskell risc-v veldt

Last synced: 18 Dec 2024

https://github.com/community-pio-ch32v/platform-ch32v

PlatformIO platform for CH32V RISC-V chips (CH32V003, CH32V103, CH32V20x, CH32V30x, CH32X035) and CH56x, CH57x, CH58x, CH59x

ble ch32v firmware microcontroller platformio platformio-platform risc-v

Last synced: 17 Dec 2024