Projects in Awesome Lists tagged with xilinx

https://github.com/open-sdr/openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

802-11 ad9361 analog-devices csma dma fpga hardware hls ieee80211 linux mac80211 ofdm openwifi sdr software-defined-radio verilog wifi xilinx xilinx-fpga zynq

Last synced: 13 May 2025

https://github.com/leiwang1999/fpga

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga pynq verilog vivado xilinx

Last synced: 27 Jan 2026

https://github.com/LeiWang1999/FPGA

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga pynq verilog vivado xilinx

Last synced: 14 Mar 2025

https://github.com/pconst/basic_verilog

Must-have verilog systemverilog modules

altera debounce delay encoder fifo fpga hls pwm spi-interface spi-master synchronizer tcl uart uart-controller uart-protocol uart-receiver uart-tx uart-verilog verilog xilinx

Last synced: 27 Jan 2026

https://github.com/pConst/basic_verilog

Must-have verilog systemverilog modules

altera debounce delay encoder fifo fpga hls pwm spi-interface spi-master synchronizer tcl uart uart-controller uart-protocol uart-receiver uart-tx uart-verilog verilog xilinx

Last synced: 14 Mar 2025

https://github.com/xilinx/brevitas

Brevitas: neural network quantization in PyTorch

brevitas deep-learning fpga hardware-acceleration neural-networks ptq pytorch qat quantization xilinx

Last synced: 11 Oct 2025

https://github.com/trabucayre/openfpgaloader

Universal utility for programming FPGA

arty bitstream cyclone fpga gowin intel lattice trenz-gowin-littlebee xilinx

Last synced: 14 May 2025

https://github.com/Xilinx/brevitas

Brevitas: neural network quantization in PyTorch

brevitas deep-learning fpga hardware-acceleration neural-networks ptq pytorch qat quantization xilinx

Last synced: 23 Apr 2025

https://github.com/hdl-util/hdmi

Send video/audio over HDMI on an FPGA

altera audio dvi fpga hdlmake hdmi intel quartus systemverilog video vivado xilinx

Last synced: 25 Jan 2026

https://github.com/trabucayre/openFPGALoader

Universal utility for programming FPGA

arty bitstream cyclone fpga gowin intel lattice trenz-gowin-littlebee xilinx

Last synced: 26 Mar 2025

https://github.com/ultraembedded/biriscv

32-bit Superscalar RISC-V CPU

artix-7 asic branch-prediction coremark cpu fpga in-order linux pipelined-processors risc-v riscv-linux rv32i rv32im superscalar verilator verilog xilinx

Last synced: 04 Apr 2025

https://github.com/eugene-tarassov/vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

arty-a7 boom fpga genesys2 kc705 linux nexys-video risc-v riscv rocketchip vc707 vivado xilinx

Last synced: 22 Apr 2025

https://github.com/cr4sh/s6_pcie_microblaze

PCI Express DIY hacking toolkit for Xilinx SP605. This repository is also home of Hyper-V Backdoor and Boot Backdoor, check readme for links and info

backdoor dma fpga hyper-v hypervisor kernel microblaze pci-e rootkit uefi xilinx

Last synced: 12 Apr 2025

https://github.com/f4pga/prjxray

Documenting the Xilinx 7-series bit-stream format.

artix artix7 bitstream fpga fuzzer kintex7 symbiflow toolchain tools vivado xilinx xilinx-fpga

Last synced: 22 Apr 2025

https://github.com/Cr4sh/s6_pcie_microblaze

PCI Express DIY hacking toolkit for Xilinx SP605. This repository is also home of Hyper-V Backdoor and Boot Backdoor, check readme for links and info

backdoor dma fpga hyper-v hypervisor kernel microblaze pci-e rootkit uefi xilinx

Last synced: 10 Apr 2025

https://github.com/open-sdr/openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

ad9361 analog-devices csma dma fpga hardware hls ieee80211 linux mac80211 ofdm rtl sdr software-defined-radio verilog vhdl wi-fi xilinx zynq

Last synced: 15 May 2025

https://github.com/olofk/edalize

An abstraction library for interfacing EDA tools

altera eda fossi fpga ghdl icarus-verilog icestorm lattice modelsim riviera-pro simulation spyglass synthesis systemverilog verilator verilog vhdl vivado xilinx yosys

Last synced: 14 May 2025

https://github.com/VLSI-EDA/PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

altera asic fpga hardware-designs hardware-libraries hardware-modules lattice osvvm poc-library python regression-testing simulation synthesis testbenches uvvm verification vhdl vlsi vunit xilinx

Last synced: 22 Apr 2025

https://github.com/xilinx/vitis_accel_examples

Vitis_Accel_Examples

acap alveo fpga-programming soc vitis xilinx zynq

Last synced: 18 Feb 2026

https://github.com/trivialmips/nontrivial-mips

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

cpu fpga fpga-soc fpga-soc-linux mips systemverilog xilinx

Last synced: 22 Apr 2025

https://github.com/ZipCPU/wb2axip

Bus bridges and other odds and ends

axi-bus fpga gplv3 wishbone wishbone-bus xilinx xilinx-vivado

Last synced: 22 Apr 2025

https://github.com/jofrfu/tinytpu

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

assembly embedded-systems fpga fpga-accelerator hardware-acceleration hardware-architectures hardware-description-language hardware-designs internet-of-things iot ip-core linux tensor tensorflow tpu verilog vhdl vivado xilinx zynq

Last synced: 07 Apr 2025

https://github.com/f32c/f32c

A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz

altera arduino fpga lattice mips riscv xilinx

Last synced: 21 Apr 2025

https://github.com/xilinx/sdaccel_examples

SDAccel Examples

aws c cpp fpga nimbix opencl sdaccel sdx xilinx

Last synced: 11 Oct 2025

https://github.com/Xilinx/SDAccel_Examples

SDAccel Examples

aws c cpp fpga nimbix opencl sdaccel sdx xilinx

Last synced: 09 Jul 2025

https://github.com/definelicht/hlslib

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

cmake fpga high-level-synthesis hpc intel-fpga intel-fpga-opencl sdaccel vitis vivado-hls xilinx

Last synced: 26 Jan 2026

https://github.com/xilinx/chaidnn

HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs

alexnet deep-neural-networks dnn embedded-vision googlenet inference xilinx xilinx-ultrascale-mpsocs

Last synced: 11 Oct 2025

https://github.com/Xilinx/RapidWright

Build Customized FPGA Implementations for Vivado

fpga rapidwright vivado xilinx

Last synced: 21 Apr 2025

https://github.com/tymonx/logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

asic cmake cpp fpga hdl modelsim quartus rtl systemc systemverilog testing-rtl unit-tests uvm verification verilator verilog vivado xilinx

Last synced: 14 Apr 2025

https://github.com/xilinx/xup_vitis_network_example

VNx: Vitis Network Examples

alveo alveo-card networking vitis vitis-network vnx xilinx

Last synced: 11 Oct 2025

https://github.com/fischermoseley/manta

A configurable and approachable tool for FPGA debugging and rapid prototyping.

debug fpga icestick icestorm verilog xilinx

Last synced: 08 Apr 2026

https://github.com/xtra-computing/thundergp

HLS-based Graph Processing Framework on FPGAs

accelerators fpgas graph-analytic-algorithm graph-processing hls programmability xilinx

Last synced: 13 Apr 2025

https://github.com/19801201/SpinalHDL_CNN_Accelerator

CNN accelerator implemented with Spinal HDL

cnn fpga object-detection spinalhdl xilinx yolo

Last synced: 21 Apr 2025

https://github.com/UCLA-VAST/AutoBridge

[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.

floorplan fpga frequency hls-compilation hls-designs vivado-hls xilinx

Last synced: 21 Apr 2025

https://github.com/z4yx/petalinux-docker

Dockerfile to build docker images with Petalinux (Tested on version 2018.3~2021.1)

docker petalinux xilinx

Last synced: 13 Apr 2025

https://github.com/trivialmips/TrivialMIPS

MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support

cpu fpga fpga-soc mips systemverilog xilinx

Last synced: 22 Apr 2025

https://github.com/nxbyte/ARM-LEGv8

Verilog Implementation of an ARM LEGv8 CPU

arm arm-legv8-simulator forwarding-unit hazard-detection hennessy isa ldr legv8-arm multi-cycle patterson pipeline-cpu single-cycle verilog vivado xilinx

Last synced: 21 Jul 2025

https://github.com/hukenovs/intfftk

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

altera cooley-tukey-fft digital-signal-processing dsp fast-convolutions fast-fourier-transform fft fpga integer-arithmetic radix-2 route-optimization verilog vhdl vivado xilinx

Last synced: 14 Feb 2026

https://github.com/stnolting/neorv32-setups

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

fpga ghdl intel lattice neorv32 risc-v soc verilog vhdl xilinx yosys

Last synced: 25 Jan 2026

https://github.com/chipsalliance/yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.

eda f4pga fpga toolchain xilinx xilinx-fpga yosys yosys-plugin

Last synced: 21 Jan 2026

https://github.com/hex-five/multizone-sdk

MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn't define TrustZone-like primitives to provide hardware separation. To shield critical functionality from untrusted third-party components, MultiZone provides hardware-enforced, software-defined separation of multi

attestation container digilent-arty-board firmware fpga freertos hypervisor microkernel multizone risc-v root-of-trust secure-boot secure-element security sifive tee trusted-computing trusted-execution-environment trustzone xilinx

Last synced: 17 Apr 2025

https://github.com/paebbels/json-for-vhdl

A JSON library implemented in VHDL.

fileformat fpga ghdl json lattice modelsim parser questasim simulation synthesis vhdl xilinx

Last synced: 29 Jul 2025

https://github.com/cr4sh/pico_dma

Autonomous pre-boot DMA attack hardware implant for M.2 slot based on PicoEVB development board

axi-dma backdoor dma fpga implant microblaze pci-e uefi xilinx

Last synced: 09 Apr 2025

https://github.com/themperek/cocotb-vivado

Limited python / cocotb interface to Xilinx/AMD Vivado simulator.

cocotb python simulation verification vivado xilinx

Last synced: 06 Apr 2026

https://github.com/halfmanhalftaco/fpga-docker

Tools for running FPGA vendor toolchains with Docker

altera fpga lattice quartus verilog vhdl xilinx

Last synced: 06 Apr 2025

https://github.com/BrianHGinc/BrianHG-DDR3-Controller

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

altera ddr3 fpga hdl intel lattice systemverilog testbenches verilog xilinx

Last synced: 15 Jun 2025

https://github.com/f4pga/prjxray-db

Project X-Ray Database: XC7 Series

artix artix7 bitset database fpga kintex7 prjxray symbiflow toolchain tools xilinx xilinx-fpga

Last synced: 22 Jul 2025

https://github.com/xilinx/pynq_composable_pipeline

PYNQ Composabe Overlays

composable fpga pynq xilinx

Last synced: 18 Feb 2026

https://github.com/cr4sh/zc_pcie_dma

DMA attacks over PCI Express based on Xilinx Zynq-7000 series SoC

axi-dma dma fpga kernel linux pci-e xilinx zynq

Last synced: 09 Apr 2025

https://github.com/duskwuff/Xilinx-ISE-Makefile

An example of how to use the Xilinx ISE toolchain from the command line

fpga xilinx xilinx-ise

Last synced: 20 Mar 2025

https://github.com/hukenovs/fp23fftk

Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).

altera chirp convolution convolution-filter cooley-tukey-fft digital-signal-processing dsp fast-convolutions fast-fourier-transform fft floating-point fpga frequency-analysis ieee754 matlab octave radix-2 verilog vhdl xilinx

Last synced: 15 May 2025

https://github.com/MJoergen/HyperRAM

Portable HyperRAM controller

altera artix avalon fpga hyperram intel lattice modelsim quartus questa questasim vhdl vivado xilinx

Last synced: 22 Apr 2025

https://github.com/xilinx/alveo-pynq

Introductory examples for using PYNQ with Alveo

alveo aws-f1 pynq xilinx

Last synced: 11 Oct 2025

https://github.com/tymonx/virtio

Virtio implementation in SystemVerilog

cmake fpga hdl model quartus rtl systemc systemverilog verilator verilog virtio vivado xilinx

Last synced: 08 Feb 2026

https://github.com/jeffdecola/my-verilog-examples

A place to keep my synthesizable verilog examples.

asic asic-design fpga gtkwave hardware hardware-architecture hardware-description-language hdl iverilog simulator synthesis synthesize systemverilog verilog verilog-simulator vivado waveform xilinx

Last synced: 17 Feb 2026

https://github.com/Elphel/eddr3

mirror of https://git.elphel.com/Elphel/eddr3

ddr ddr3 fpga memory-controller open-core verilog xilinx zynq

Last synced: 22 Jul 2025

https://github.com/xilinx/xup_fpga_vivado_flow

AMD Xilinx University Program Vivado tutorial

fpga hardware vivado xilinx

Last synced: 15 Feb 2026

https://github.com/spcl/apfp

FPGA acceleration of arbitrary precision floating point computations.

arbitrary-precision bignum fpga gmp high-level-synthesis high-performance-computing hls hpc mpfr multiple-precision vitis vivado-hls xilinx

Last synced: 07 Apr 2025

https://github.com/MeowLucian/SDR_FM_Radio

:radio: Using Software Designed Radio to transmit & receive FM signal

ad9361 analog-devices demodulation fm fmcomms fmcomms3 modulation radio sdr simulink simulink-model station xilinx xilinx-zynq zedboard zynq

Last synced: 06 Apr 2025

https://github.com/ahirsharan/32-Bit-Floating-Point-Adder

Verilog Implementation of 32-bit Floating Point Adder

verilog vlsi xilinx

Last synced: 22 Apr 2025

https://github.com/hukenovs/tcl_for_fpga

TCL scripts for FPGA (Xilinx)

clock-groups fpga hdl synth tcl tcl-scripts vivado xilinx

Last synced: 30 Dec 2025

https://github.com/z4yx/vivado-docker

Dockerfile with Vivado for CI

docker fpga vivado xilinx

Last synced: 21 Apr 2025

https://github.com/geraked/verilog-rle

Verilog Implementation of Run Length Encoding for RGB Image Compression

compression-algorithm computer-engineering fpga fpga-programming geraked image-compression image-processing ise matlab rabist rle rle-compression-algorithm run-length-encoding student-project verilog verilog-code verilog-hdl xilinx xilinx-fpga yazd-university

Last synced: 10 Mar 2026

https://github.com/teddy-van-jerry/sdr-psk-fpga

Dual-Mode PSK Transceiver on SDR With FPGA

amd bpsk costas-loop demodulation fpga gardner modulation psk qpsk sdr software-defined-radio synchronization transceiver verilog vivado xilinx zynq zynq-7000 zynq-7020

Last synced: 06 Jan 2026

https://github.com/benpye/nix-fpga-tools

fpga nix nix-flake xilinx

Last synced: 30 Apr 2025

https://github.com/henrikbrixandersen/elf-bootloader

SPI ELF bootloader for Xilinx Microblaze processors

bootloader elf spi vivado xilinx xilinx-sdk xilinx-vivado

Last synced: 11 Apr 2025

https://github.com/chili-chips-ba/openxc7-tetrisaraj

Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.

basys3 fpga gamedev nextpnr open-source rtl soc tetris-game verilog-hdl xc7a35t xilinx yosys

Last synced: 12 Jan 2026

https://github.com/lvgl/lv_port_xilinx_zedboard_vitis

This repository contains a template AMP project for the Zedboard using VGA, FreeRTOS, LVGL and USB peripherals

amd digilent embedded freertos lvgl mouse ntp tcp touchscreen usb vga vitis vivado xilinx zedboard

Last synced: 05 Apr 2025

https://github.com/pothosware/pothoszynq

DMA source and sink blocks for Xilinx Zynq FPGAs

dma fpga pothos pothos-framework vivado xilinx zynq

Last synced: 05 Mar 2025

https://github.com/b1f6c1c4/deep-darkfantasy

Global Dark Mode for ALL apps on ANY platforms.

dark-mode dark-mode-toggle dark-theme fpga verilog verilog-hdl vivado xilinx zynq zynq-7000

Last synced: 23 Jan 2026

https://github.com/stv0g/xilinx-hw-server-docker

Run a Xilinx hw_server in a Docker container

docker xilinx

Last synced: 22 Jun 2025

https://github.com/perehinik/sdram_controller

Verilog SDR SDRAM controller for FPGA Xilinx and Lattice

fpga lattice sdram verilog xilinx

Last synced: 27 Jan 2026

https://github.com/gergoerdi/brainfuck-cpu-fpga

A CPU that uses Brainfuck as its machine code

brainfuck fpga haskell kansas-lava microprocessor papilio xilinx

Last synced: 26 Jul 2025

https://github.com/chipsalliance/f4pga-bitstream-viewer

Tool for graphically viewing FPGA bitstream files and their connection to FASM features.

bitstream bitstream-viewer symbiflow xilinx

Last synced: 06 Apr 2025

https://github.com/defano/digital-design

An introduction to integrated circuit design with Verilog and the Papilio Pro development board.

digital-design papilio papilio-board papilio-hardware verilog xilinx

Last synced: 02 Feb 2026

https://github.com/anthony-bernaert/ftdi-jtag-programmer

FTDI-based JTAG Programmer Circuit for FPGAs

altera fpga ftdi intel-fpga jtag lattice pcb-design programmer serial-port uart usb xilinx

Last synced: 08 Apr 2026

https://github.com/perehinik/logic_analyzer_fpga_config

Vivado project for Xilinx Artix FPGA, used in logic analyzer

fpga verilog vivado xilinx

Last synced: 26 Jan 2026

https://github.com/bucknalla/ip_cores

Verilog IP Cores & Tests

ofdm rf vivado xilinx

Last synced: 23 Oct 2025

https://github.com/hukenovs/adc_configurator

ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)

adc adc-configurator altera analog-signals cic dac ddc ddr dds digital-signal-processing dsp fir jesd204b serdes-mode serial-interface vhdl xilinx

Last synced: 02 Jan 2026

https://github.com/raczben/tco_study

Case study of synchronous FPGA signaling by adjusting the output timing

clock-to-output constraint fpga synchronous tco timing ultrascale vivado xilinx

Last synced: 01 Apr 2026

https://github.com/parthpower/axi_uartlite_pynq

PYNQ-Z1 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx

pynq-z1 python uart xilinx

Last synced: 12 Apr 2025

https://github.com/hukenovs/fp32_logic

Floating point FP32 core HDL. For Xilinx FPGAs. Include base converters and some math functions.

altera digital-signal-processing dsp floating-point fpga ieee-754 ieee754 integer-arithmetic verilog vhdl xilinx

Last synced: 17 Mar 2026

https://github.com/jmduarte/hls_hls4ml_tutorial

HLS & hls4ml Tutorial

fpga fpga-firmware fpga-programming high-energy-physics high-level-synthesis hls hls4ml machine-learning particle-physics vitis vivado vivado-hls xilinx xilinx-fpga

Last synced: 11 Sep 2025

https://github.com/risto97/zturn_linux

Building linux kernel and u-boot for MYIR Z-Turn 7020 Zynq Board

fpga linux-kernel u-boot vivado xilinx zturn zynq

Last synced: 25 Jun 2025

https://github.com/kampi/zybo

Miscellaneous things and projects for my ZYBO and ZYNQ devices.

amd arm c cpp fpga fpga-programming linux vhdl wsl-ubuntu wsl2 xilinx zybo zynq

Last synced: 04 Oct 2025

https://github.com/gergoerdi/chip8-papilio

FPGA implementation of the Chip8 platform, in Kansas Lava

chip8 fpga haskell kansas-lava microprocessor papilio retro xilinx

Last synced: 19 Apr 2025

https://github.com/pothosware/pothosfpga

Pothos FPGA computational offload and buffer integration support

axi fpga pothos pothos-framework stream xilinx

Last synced: 05 Mar 2026

https://github.com/kampi/zybo-linux

A complete Linux project for the ZYBO. This project helps me during my first steps with embedded Linux. You can find anything necessary to run your own embedded Linux on your ZYBO here.

c cpp linux vivado xilinx yocto zybo zybo-board zybo-linux zynq