Ecosyste.ms: Awesome
An open API service indexing awesome lists of open source software.
Projects in Awesome Lists tagged with xilinx
A curated list of projects in awesome lists tagged with xilinx .
https://github.com/pconst/basic_verilog
Must-have verilog systemverilog modules
altera debounce delay encoder fifo fpga hls pwm spi-interface spi-master synchronizer tcl uart uart-controller uart-protocol uart-receiver uart-tx uart-verilog verilog xilinx
Last synced: 30 Sep 2024
https://github.com/pConst/basic_verilog
Must-have verilog systemverilog modules
altera debounce delay encoder fifo fpga hls pwm spi-interface spi-master synchronizer tcl uart uart-controller uart-protocol uart-receiver uart-tx uart-verilog verilog xilinx
Last synced: 30 Jul 2024
https://github.com/Xilinx/brevitas
Brevitas: neural network quantization in PyTorch
brevitas deep-learning fpga hardware-acceleration neural-networks ptq pytorch qat quantization xilinx
Last synced: 02 Aug 2024
https://github.com/trabucayre/openFPGALoader
Universal utility for programming FPGA
arty bitstream cyclone fpga gowin intel lattice trenz-gowin-littlebee xilinx
Last synced: 31 Jul 2024
https://github.com/ultraembedded/biriscv
32-bit Superscalar RISC-V CPU
artix-7 asic branch-prediction coremark cpu fpga in-order linux pipelined-processors risc-v riscv-linux rv32i rv32im superscalar verilator verilog xilinx
Last synced: 02 Aug 2024
https://github.com/eugene-tarassov/vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
arty-a7 boom fpga genesys2 kc705 linux nexys-video risc-v riscv rocketchip vc707 vivado xilinx
Last synced: 02 Aug 2024
https://github.com/Cr4sh/s6_pcie_microblaze
PCI Express DIY hacking toolkit for Xilinx SP605. This repository is also home of Hyper-V Backdoor and Boot Backdoor, check readme for links and info
backdoor dma fpga hyper-v hypervisor kernel microblaze pci-e rootkit uefi xilinx
Last synced: 01 Aug 2024
https://github.com/olofk/edalize
An abstraction library for interfacing EDA tools
altera eda fossi fpga ghdl icarus-verilog icestorm lattice modelsim riviera-pro simulation spyglass synthesis systemverilog verilator verilog vhdl vivado xilinx yosys
Last synced: 02 Aug 2024
https://github.com/trivialmips/nontrivial-mips
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
cpu fpga fpga-soc fpga-soc-linux mips systemverilog xilinx
Last synced: 02 Aug 2024
https://github.com/VLSI-EDA/PoC
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
altera asic fpga hardware-designs hardware-libraries hardware-modules lattice osvvm poc-library python regression-testing simulation synthesis testbenches uvvm verification vhdl vlsi vunit xilinx
Last synced: 02 Aug 2024
https://github.com/ZipCPU/wb2axip
Bus bridges and other odds and ends
axi-bus fpga gplv3 wishbone wishbone-bus xilinx xilinx-vivado
Last synced: 02 Aug 2024
https://github.com/jofrfu/tinytpu
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
assembly embedded-systems fpga fpga-accelerator hardware-acceleration hardware-architectures hardware-description-language hardware-designs internet-of-things iot ip-core linux tensor tensorflow tpu verilog vhdl vivado xilinx zynq
Last synced: 29 Sep 2024
https://github.com/Xilinx/RapidWright
Build Customized FPGA Implementations for Vivado
fpga rapidwright vivado xilinx
Last synced: 02 Aug 2024
https://github.com/19801201/SpinalHDL_CNN_Accelerator
CNN accelerator implemented with Spinal HDL
cnn fpga object-detection spinalhdl xilinx yolo
Last synced: 02 Aug 2024
https://github.com/UCLA-VAST/AutoBridge
[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
floorplan fpga frequency hls-compilation hls-designs vivado-hls xilinx
Last synced: 02 Aug 2024
https://github.com/z4yx/petalinux-docker
Dockerfile to build docker images with Petalinux (Tested on version 2018.3~2021.1)
Last synced: 02 Aug 2024
https://github.com/trivialmips/TrivialMIPS
MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
cpu fpga fpga-soc mips systemverilog xilinx
Last synced: 02 Aug 2024
https://github.com/hex-five/multizone-sdk
MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn't define TrustZone-like primitives to provide hardware separation. To shield critical functionality from untrusted third-party components, MultiZone provides hardware-enforced, software-defined separation of multi
attestation container digilent-arty-board firmware fpga freertos hypervisor microkernel multizone risc-v root-of-trust secure-boot secure-element security sifive tee trusted-computing trusted-execution-environment trustzone xilinx
Last synced: 01 Aug 2024
https://github.com/paebbels/json-for-vhdl
A JSON library implemented in VHDL.
fileformat fpga ghdl json lattice modelsim parser questasim simulation synthesis vhdl xilinx
Last synced: 01 Oct 2024
https://github.com/duskwuff/Xilinx-ISE-Makefile
An example of how to use the Xilinx ISE toolchain from the command line
Last synced: 31 Jul 2024
https://github.com/Elphel/eddr3
mirror of https://git.elphel.com/Elphel/eddr3
ddr ddr3 fpga memory-controller open-core verilog xilinx zynq
Last synced: 09 Aug 2024
https://github.com/MeowLucian/SDR_FM_Radio
:radio: Using Software Designed Radio to transmit & receive FM signal
ad9361 analog-devices demodulation fm fmcomms fmcomms3 modulation radio sdr simulink simulink-model station xilinx xilinx-zynq zedboard zynq
Last synced: 01 Aug 2024
https://github.com/ahirsharan/32-Bit-Floating-Point-Adder
Verilog Implementation of 32-bit Floating Point Adder
Last synced: 02 Aug 2024
https://github.com/xilover/iot-and-edge-computing
Hands-on learning experience in IoT, edge computing, and embedded systems using a variety of platforms such as microcontrollers (nRF, STM32, ESP32), FPGAs (Xilinx), and SoCs (Raspberry Pi, Zynq).
aws-iot azure-iot ble circuit-design edge-computing esp32 fpga iot mqtt nrf pynq-z2 raspberry-pi rtos stm32 system-on-chip verilog vhdl vivado xilinx xilinx-zynq
Last synced: 29 Sep 2024
https://github.com/paebbels/pyipcmi
A Python-based IP Core Management Infrastructure.
altera database infrastructure intel ip-core modelsim python3 quartus-prime questasim riviera-pro simulation synthesis vhdl vhdl-verification xilinx xilinx-vivado
Last synced: 01 Oct 2024
https://github.com/paebbels/picoblaze-examples
PicoBlaze-Examples offers reference and example designs for the PicoBlaze-Libary.
fpga picoblaze-library poc-library synthesis vhdl xilinx
Last synced: 01 Oct 2024
https://github.com/salehjg/DGCNN-on-FPGA
PLEASE USE THE NEW REPO https://github.com/salehjg/DeepPoint-V2-FPGA . The deprecated in-order-queue-based repository for "DGCNN on FPGA: Acceleration of The Point CloudClassifier Using FPGAs".
classification deep-learning dgcnn fpga heterogeneous hls point-cloud xilinx
Last synced: 31 Jul 2024
https://github.com/tristanpenman/fpga-basics
Some simple FPGA projects, targeting Xilinx Spartan 6 based Papilio Pro boards
Last synced: 02 Oct 2024
