Ecosyste.ms: Awesome
An open API service indexing awesome lists of open source software.
Projects in Awesome Lists by ZipCPU
A curated list of projects in awesome lists by ZipCPU .
https://github.com/ZipCPU/zipcpu
A small, light weight, RISC CPU soft core
cpu cross-compiler fpga risc-cpu soft-core verilator verilog wishbone wishbone-bus zipcpu
Last synced: 30 Jul 2024
https://github.com/ZipCPU/wb2axip
Bus bridges and other odds and ends
axi-bus fpga gplv3 wishbone wishbone-bus xilinx xilinx-vivado
Last synced: 02 Aug 2024
https://github.com/ZipCPU/wbuart32
A simple, basic, formally verified UART controller
fpga serialport uart uart-verilog verilator verilog wishbone wishbone-bus
Last synced: 30 Jul 2024
https://github.com/ZipCPU/vgasim
A Video display simulator
fpga gplv3 gtkmm verilator verilog vga video video-simulator
Last synced: 02 Aug 2024
https://github.com/ZipCPU/sdspi
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
axi emmc fpga sd-card sd-interface sdio spi-interface verilator verilog verilog-components wishbone wishbone-bus
Last synced: 02 Aug 2024
https://github.com/ZipCPU/qspiflash
A set of Wishbone Controlled SPI Flash Controllers
Last synced: 02 Aug 2024
https://github.com/ZipCPU/wbscope
A wishbone controlled scope for FPGA's
debugging-tools fpga verilator verilog wishbone wishbone-bus
Last synced: 02 Aug 2024
https://github.com/ZipCPU/sdr
A basic Soft(Gate)ware Defined Radio architecture
Last synced: 09 Aug 2024
https://github.com/ZipCPU/fftdemo
A demonstration showing how several components can be compsed to build a simulated spectrogram
Last synced: 09 Aug 2024
https://github.com/ZipCPU/zipversa
A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure
Last synced: 09 Aug 2024