Projects in Awesome Lists tagged with verilator
A curated list of projects in awesome lists tagged with verilator .
https://github.com/verilator/verilator
Verilator open-source SystemVerilog simulator and lint system
compilers cpp rtl system-verilog systemc verilator verilog verilog-simulator
Last synced: 21 Oct 2025
https://github.com/ultraembedded/riscv
RISC-V CPU Core (RV32IM)
asic cpu fpga pipeline-processor risc-v riscv-linux rv32i rv32im verification verilator verilog
Last synced: 22 Mar 2025
https://github.com/ZipCPU/zipcpu
A small, light weight, RISC CPU soft core
cpu cross-compiler fpga risc-cpu soft-core verilator verilog wishbone wishbone-bus zipcpu
Last synced: 14 Mar 2025
https://github.com/ultraembedded/biriscv
32-bit Superscalar RISC-V CPU
artix-7 asic branch-prediction coremark cpu fpga in-order linux pipelined-processors risc-v riscv-linux rv32i rv32im superscalar verilator verilog xilinx
Last synced: 04 Apr 2025
https://github.com/chipsalliance/cores-veer-eh1
VeeR EH1 core
ahb-lite asic-design axi4 fpga fusesoc open-source-hardware processor risc risc-v riscv riscv32 rtl veer verilator western-digital
Last synced: 24 Jul 2025
https://github.com/chipsalliance/Cores-VeeR-EH1
VeeR EH1 core
ahb-lite asic-design axi4 fpga fusesoc open-source-hardware processor risc risc-v riscv riscv32 rtl veer verilator western-digital
Last synced: 22 Apr 2025
https://github.com/ultraembedded/cores
Various HDL (Verilog) IP Cores
asic audio fpga i2s rtl sdram spi sram uart usb verilator verilog verilog-components verilog-hdl
Last synced: 01 Mar 2025
https://github.com/olofk/edalize
An abstraction library for interfacing EDA tools
altera eda fossi fpga ghdl icarus-verilog icestorm lattice modelsim riviera-pro simulation spyglass synthesis systemverilog verilator verilog vhdl vivado xilinx yosys
Last synced: 14 May 2025
https://github.com/mshr-h/vscode-verilog-hdl-support
HDL support for VS Code
bluespec-systemverilog ctags hacktoberfest icarus-verilog iverilog language-server-client modelsim svls systemverilog systemverilog-support verilator verilog verilog-hdl vivado vscode
Last synced: 08 Apr 2025
https://github.com/tymonx/logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
asic cmake cpp fpga hdl modelsim quartus rtl systemc systemverilog testing-rtl unit-tests uvm verification verilator verilog vivado xilinx
Last synced: 14 Apr 2025
https://github.com/chipsalliance/cores-veer-el2
VeeR EL2 Core
ahb-lite asic-design axi4 el2 fpga fusesoc open-source-hardware processor risc-v riscv riscv32 rtl verilator western-digital
Last synced: 10 Apr 2025
https://github.com/ZipCPU/wbuart32
A simple, basic, formally verified UART controller
fpga serialport uart uart-verilog verilator verilog wishbone wishbone-bus
Last synced: 14 Mar 2025
https://github.com/dpretet/async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
asic asic-design async cdc cross-clock-domain fifo fifo-cache fifo-queue fpga hdl icarus-verilog synthesis verification verilator verilog verilog-hdl
Last synced: 22 Apr 2025
https://github.com/chipsalliance/Cores-VeeR-EL2
VeeR EL2 Core
ahb-lite asic-design axi4 el2 fpga fusesoc open-source-hardware processor risc-v riscv riscv32 rtl verilator western-digital
Last synced: 02 Apr 2025
https://github.com/ZipCPU/vgasim
A Video display simulator
fpga gplv3 gtkmm verilator verilog vga video video-simulator
Last synced: 22 Apr 2025
https://github.com/ZipCPU/sdspi
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
axi emmc fpga sd-card sd-interface sdio spi-interface verilator verilog verilog-components wishbone wishbone-bus
Last synced: 22 Apr 2025
https://github.com/ZipCPU/openarty
An Open Source configuration of the Arty platform
arty fpga fpga-soc verilator wishbone wishbone-bus zipcpu
Last synced: 21 Jul 2025
https://github.com/dpretet/svut
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
flow foss gtkwave icarus-verilog mit-license python simulation simulator surfer svut systemverilog tdd tdd-utilities testcase vcd verification-methodologies verilator verilog
Last synced: 22 Apr 2025
https://github.com/chili-chips-ba/wireguard-fpga
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
cocotb embedded fpga iss risc-v rtl verilator verilog vpn vproc wireguard
Last synced: 09 Apr 2025
https://github.com/ZipCPU/wbscope
A wishbone controlled scope for FPGA's
debugging-tools fpga verilator verilog wishbone wishbone-bus
Last synced: 22 Apr 2025
https://github.com/ben-marshall/croyde-riscv
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
cpu crypto cryptography formal-verification micro-controller microcontroller mit-license risc risc-v riscv64 systemverilog verilator verilog yosys
Last synced: 05 Jan 2026
https://github.com/sgherbst/svreal
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
fixed-point floating-point icarus icarus-verilog irun iverilog ncsim simulation synthesis synthesizable systemverilog vcs verilator verilog vivado xcelium xrun
Last synced: 11 May 2025
https://github.com/ethanuppal/marlin
🦀 No nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl
hardware rust simulation testbench testing verilator verilog
Last synced: 09 Apr 2025
https://github.com/microdynamics-cpu/tree-core-cpu
:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
chisel cpu processor riscv rt-thread rtl scala softcore verilator
Last synced: 21 Jul 2025
https://github.com/wyvernsemi/mem_model
High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
avalon axi cosimulation dpi-c ghdl memory-model nvc pli questasim simulation test-bench verilator verilog verilog-components verilog-testbenches vhdl vivado-simulator
Last synced: 31 Mar 2025
https://github.com/tum-ei-eda/vrtlmod
vRTLmod modifies Verilator generated RTL simulation code for faul-injection purposes. It transforms source code with the help of LLVM/Clang-Tools and generates a fault injection API.
clang fault-injection llvm register-transfer-level verilator
Last synced: 06 Sep 2025
https://github.com/maxxsoft/bossa
BOOM's Simulation Accelerator.
accelerator boom chipyard chisel firrtl risc-v riscv rocket rocket-chip rtl simulation soc verilator
Last synced: 22 Apr 2025
https://github.com/jasonbrave/pci-edu
SystemVerilog implemention of QEMU PCI edu device
pci pci-bus pci-devices systemverilog verilator verilog
Last synced: 19 Sep 2025
https://github.com/rismicrodevices/rmr8pm3001a
Taurus 3001 RISC-V 64-bit Privileged Minimal System Processor for T110/T28 ASIC
jasse out-of-order risc-v rv64 rv64i verilator verilog verilog-project ysyx3 ysyx4
Last synced: 23 Jun 2025
https://github.com/sysprog21/vga-nyancat
Hardware-accelerated Nyancat animation on VGA display, implemented in Verilog RTL
Last synced: 28 Oct 2025
https://github.com/sinakarvandi/hardware-design-stack
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
asic asic-design chisel chisel3 fpga gtkwave modelsim netlist openlane openram verilator verilog vhdl vitis vitis-hls vivado vivado-hls
Last synced: 26 Oct 2025
https://github.com/HEP-SoC/SoCMake
CMake based hardware build system
asic build-automation build-system cmake fpga integrated-circuits system-on-chip systemverilog verilator verilog vhdl vhdl-language
Last synced: 19 Jul 2025
https://github.com/risto97/pygears-uvm
SystemC UVM environment generator for PyGears components. RTL simulated with Verilator
pygears systemc systemc-uvm-generator uvm verification verilator
Last synced: 10 Oct 2025
https://github.com/weisrc/web-verilog-poc
Running verilog on hardware, desktop and the web
emscripten fpga poc systemverilog verilator verilog wasm webassembly
Last synced: 24 Oct 2025
https://github.com/yasnakateb/chipyardintegration
😱 RoCC Accelerator Integration with Chipyard
accelerators chipyard chisel chisel3 computer-architecture hardware hardware-acceleration integration risc-v rocc rocket rocket-chip sbt scala simulation verilator
Last synced: 15 Apr 2025
https://github.com/muhammadtalhasami/rv32i_single_cycle
This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.
fetch-stage-pipeline gtkwave hardware-designs muhammadtalhasami-github- pipeline-processor risc-v-assembly risc-v-pipeline risc-v-processor risc-v-processor-images rv32i rv32i-processor single-cycle-processor single-cycle-processor-gtkwave-image system-verilog system-verilog-codes verilator verilog verilog-code-examples verilog-codes vhdl
Last synced: 09 Sep 2025
https://github.com/gergoerdi/clash-bounce-bench
Benchmark for various methods of simulating Clash
benchmark c clash haskell sdl2 simulation verilator verilog
Last synced: 12 Sep 2025
https://github.com/weisrc/nesv
NESystem Verilog
basys3 emscripten emulator fpga nes systemverilog verilator verilog vivado webassembly
Last synced: 01 Sep 2025
https://github.com/daulpavid/verilog_template
Boilerplate project template for verilog that includes directories for simulation, documentation, and formal verification.
cmake verilator verilog verilog-template
Last synced: 09 Oct 2025
https://github.com/nsailor/feather
A single cycle processor implementing a subset of the ARMv7 ISA.
armv7 computer-architecture digital-design systemverilog verilator
Last synced: 28 Mar 2025
https://github.com/muhammadtalhasami/axi4_lite_interface
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
axi4 axi4-lite axi4-lite-interface axi4-lite-system-verilog axi4-protocol system-verilog verilator vivado
Last synced: 12 May 2025
https://github.com/williamzhang20/digital-hardware-blocks
Fundamental Digital Logic Concepts in Verilog
Last synced: 30 Jun 2025
https://github.com/nambers/0dmips
[WIP] in-order 5-stages pipeline MIPS64r6el SoC implementation with peripheral components, simulated with verilator
mips64 systemverilog verilator
Last synced: 25 Dec 2025
https://github.com/periareon/rules_verilog
Bazel rules for Verilog synthesis
bazel bazel-rules system-verilog systemverilog systemverilog-hdl verilator verilog verilog-hdl
Last synced: 25 Nov 2025
https://github.com/coldnew/nand2tetris
My notes and impement on Nand2Tetris courses
coursearea nand2tetris personal-notes verilator verilog
Last synced: 27 Jul 2025
https://github.com/nambers/mips64
[WIP] 5-stage pipeline MIPS64 SoC implementation with peripheral components, simulated with verilator
mips64 systemverilog verilator
Last synced: 12 Mar 2025
https://github.com/rehanmq/asic-soc-ml-accelerator-verification
End-to-end ASIC SoC design and functional verification of a lightweight machine learning accelerator using SystemVerilog and UVM. Includes Python automation for test generation and result analysis. Built to simulate real-world ML silicon validation at scale.
ai-hardware asic-verification msp432 soc-design system-design systemverilog verilator
Last synced: 02 Apr 2025
