Projects in Awesome Lists tagged with netlist
A curated list of projects in awesome lists tagged with netlist .
https://github.com/nturley/netlistsvg
draws an SVG schematic from a JSON netlist
diagram elk klayjs netlist visualization yosys
Last synced: 20 Feb 2026
https://github.com/emsec/hal
HAL – The Hardware Analyzer
embedded-security fpga hal hardware integrated-circuits netlist reverse-engineering security
Last synced: 15 May 2025
https://github.com/circuitgraph/circuitgraph
Tools for working with circuits as graphs in python
boolean-circuits eda graphs netlist python satisfiability
Last synced: 11 May 2025
https://github.com/najaeda/naja
Structural Netlist API (and more) for EDA post synthesis flow development
asic cpp eda fpga netlist semiconductor verilog
Last synced: 11 May 2025
https://github.com/byuccl/spydrnet
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
cad circuit circuit-analysis circuit-design circuits computer-aided-design digital eda edif electronic-design-automation fpga fpgas hardware hardware-designs netlist netlist-parser netlists transformation transformations
Last synced: 11 May 2025
https://byuccl.github.io/spydrnet/
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
cad circuit circuit-analysis circuit-design circuits computer-aided-design digital eda edif electronic-design-automation fpga fpgas hardware hardware-designs netlist netlist-parser netlists transformation transformations
Last synced: 15 Mar 2025
https://github.com/arasgungore/netlist-solver
A MATLAB project that uses modified nodal analysis to calculate the node voltages of any analog circuit.
algorithm algorithms analog-design circuit circuit-analysis circuit-simulation circuit-simulator circuit-theory circuits circuits-simulator matlab mna modified-nodal-analysis modified-node-analysis netlist netlist-parser netlist-simulator netlists nodal-analysis node-analysis
Last synced: 12 Apr 2025
https://github.com/emsec/hal-benchmarks
Benchmark suite for HAL
hardware netlist reverse-engineering verilog vhdl
Last synced: 03 Mar 2026
https://github.com/sinakarvandi/hardware-design-stack
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
asic asic-design chisel chisel3 fpga gtkwave modelsim netlist openlane openram verilator verilog vhdl vitis vitis-hls vivado vivado-hls
Last synced: 25 Feb 2026
https://github.com/shishir-dey/vhdl-samples
Contains VHDL netlists of basic digital circuits
hardware-designs netlist testbench vhdl
Last synced: 08 Mar 2026
https://github.com/rohankalbag/logic-simulator
Course Assignment - Foundations of VLSI CAD - Autumn Semester 2022 - Indian Institute of Technology Bombay
combinational-circuit logic-simulator netlist python vlsi-cad
Last synced: 18 Apr 2026
https://github.com/tscircuit/circuit-json-to-readable-netlist
Convert Circuit JSON into a readable netlist suitable for input to AI
Last synced: 29 Sep 2025
https://github.com/muhammadtalhasami/openlane
This is my openlane repository in which we perform synthesis of our design/module.
cts- desgin-synthesis- floorplan- klayout muhammad-talha-github- muhammadtalhasami-github- netlist netlist-simulation- openlane openlane-flow openlane-github- openlanegithub- placement- rounting- synthesis
Last synced: 19 Mar 2026
https://github.com/kitanokitsune/s-expression-library-for-python
S-expression data structure parser/manipulator intended for parsing and manipulating lisp program, lisp data, netlists like EDIF and KiCAD, etc.
cad edif library lisp netlist python s-expressions
Last synced: 12 May 2026
https://github.com/jjateen/7t-sram-mcpl
This project showcases the design and simulation of a 7T MCPL SRAM using adiabatic logic for low-power efficiency, developed for ECL 312 at IIIT Nagpur. It compares the 6T and 7T SRAM designs in terms of power, energy, and stability, with simulations done in WinSpice and Microwind.
cmos cmos-circuits cmos-design layout-design microwind netlist spice
Last synced: 14 Feb 2026
https://github.com/mummanajagadeesh/cmos-inverter
CMOS inverter designed in Magic VLSI using SCMOS technology, extracted into a SPICE netlist, and simulated in ngspice. Includes layout, extraction files, and a simulation wrapper with transient analysis and waveform outputs
cmos cmos-inverter inverter layout magic-vlsi netlist ngspice nmos-pmos scmos spice vlsi
Last synced: 13 Feb 2026
https://github.com/wiresynth/wiresynth-scala
Describing components and wiring in circuit board design with presentation in Scala.
Last synced: 14 Jan 2026
