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Projects in Awesome Lists tagged with chisel
A curated list of projects in awesome lists tagged with chisel .
https://github.com/openxiangshan/xiangshan
Open-source high-performance RISC-V processor
chisel microarchitecture risc-v
Last synced: 30 Sep 2024
https://github.com/OpenXiangShan/XiangShan
Open-source high-performance RISC-V processor
chisel microarchitecture risc-v
Last synced: 30 Jul 2024
https://github.com/chipsalliance/chisel
Chisel: A Modern Hardware Design Language
chip-generator chisel chisel3 firrtl rtl scala verilog
Last synced: 30 Sep 2024
https://github.com/chipsalliance/rocket-chip
Rocket Chip Generator
chip-generator chisel riscv rocket-chip rtl scala
Last synced: 29 Sep 2024
https://github.com/riscv-boom/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
berkeley boom chisel riscv riscv-boom rocket-chip rtl scala
Last synced: 01 Oct 2024
https://github.com/ucb-bar/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
accelerators boom chip-generator chipyard chisel firesim hwacha out-of-order peripherals risc-v riscv rocket rocket-chip rtl soc superscalar
Last synced: 26 Sep 2024
https://github.com/ucb-bar/riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
Last synced: 31 Jul 2024
https://github.com/RadicalCSG/Chisel.Prototype
Work in progress prototype for the Chisel Level Editor, for Unity
bsp chisel constructive-solid-geometry csg level-design level-editor leveldesign mapping prototype realtime unity
Last synced: 02 Aug 2024
https://github.com/ucb-bar/chiseltest
The batteries-included testing and formal verification library for Chisel-based RTL designs.
chisel formal testing verification
Last synced: 02 Aug 2024
https://github.com/bu-icsg/dana
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
chisel hardware neural-network riscv rocc rocket-chip rtl
Last synced: 03 Aug 2024
https://github.com/ucb-bar/constellation
A Chisel RTL generator for network-on-chip interconnects
chisel hardware interconnect network-on-chip noc rtl soc
Last synced: 02 Aug 2024
https://github.com/chiselverify/chiselverify
A dynamic verification library for Chisel.
bus-functional-model chisel chisel-test constrained-random-verification coverage functional-coverage scala testing timed-assertions verification
Last synced: 02 Aug 2024
https://github.com/freechipsproject/diagrammer
Provides dot visualizations of chisel/firrtl circuits
chisel chisel3 firrtl visualization
Last synced: 02 Aug 2024
https://github.com/FyraLabs/chisel-operator
Kubernetes Operator for Chisel
chisel inlets inlets-pro inletsdev k8s k8s-operator kubernetes kubernetes-operator tunnel tunneling
Last synced: 01 Aug 2024
https://github.com/sifive/chisel-circt
Library to compile Chisel circuits using LLVM/MLIR (CIRCT)
Last synced: 02 Aug 2024
https://github.com/rhysd/riscv32-cpu-chisel
Learning how to make RISC-V 32bit CPU with Chisel
Last synced: 01 Oct 2024
https://github.com/microdynamics-cpu/tree-core-cpu
:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
chisel cpu processor riscv rt-thread rtl scala softcore verilator
Last synced: 08 Aug 2024
https://github.com/IBM/perfect-chisel
Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program
Last synced: 02 Aug 2024
https://github.com/wangrunji0408/rjrouter
[AFK] Hardware router in Chisel (THU Network Joint Lab 2020)
Last synced: 02 Aug 2024
