https://github.com/openxiangshan/xiangshan

Open-source high-performance RISC-V processor

chisel microarchitecture risc-v

Last synced: 12 May 2025

https://github.com/OpenXiangShan/XiangShan

Open-source high-performance RISC-V processor

chisel microarchitecture risc-v

Last synced: 14 Mar 2025

https://github.com/chipsalliance/chisel

Chisel: A Modern Hardware Design Language

chip-generator chisel chisel3 firrtl rtl scala verilog

Last synced: 12 May 2025

https://github.com/chipsalliance/rocket-chip

Rocket Chip Generator

chip-generator chisel riscv rocket-chip rtl scala

Last synced: 17 Dec 2025

https://github.com/riscv-boom/riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

berkeley boom chisel riscv riscv-boom rocket-chip rtl scala

Last synced: 14 May 2025

https://github.com/ucb-bar/chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

accelerators boom chip-generator chipyard chisel firesim hwacha out-of-order peripherals risc-v riscv rocket rocket-chip rtl soc superscalar

Last synced: 14 May 2025

https://github.com/ucb-bar/riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

chisel riscv rtl

Last synced: 16 Mar 2025

https://github.com/RadicalCSG/Chisel.Prototype

Work in progress prototype for the Chisel Level Editor, for Unity

bsp chisel constructive-solid-geometry csg level-design level-editor leveldesign mapping prototype realtime unity

Last synced: 25 Apr 2025

https://github.com/t-k-233/risc-v-single-cycle-cpu

RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel

chisel logisim risc-v verilog

Last synced: 27 Jan 2026

https://github.com/ucb-bar/chiseltest

The batteries-included testing and formal verification library for Chisel-based RTL designs.

chisel formal testing verification

Last synced: 22 Apr 2025

https://github.com/bu-icsg/dana

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

chisel hardware neural-network riscv rocc rocket-chip rtl

Last synced: 09 May 2025

https://github.com/t3l3machus/pentest-pivoting

A compact guide to network pivoting for penetration testings / CTF challenges.

burpsuite chisel double-pivoting hacking network pentesting pivoting proxy proxychains socks4 socks5 ssh sshuttle

Last synced: 08 Oct 2025

https://github.com/ucb-bar/constellation

A Chisel RTL generator for network-on-chip interconnects

chisel hardware interconnect network-on-chip noc rtl soc

Last synced: 04 Apr 2025

https://github.com/maxxsoft/fuxi

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

chisel cpu fpga riscv scala

Last synced: 17 Jun 2025

https://github.com/im-tomu/fomu-workshop

Support files for participating in a Fomu workshop

chisel fomu fomu-workshop fpga hdl litex migen riscv verilog vhdl

Last synced: 17 Jan 2026

https://github.com/chiselverify/chiselverify

A dynamic verification library for Chisel.

bus-functional-model chisel chisel-test constrained-random-verification coverage functional-coverage scala testing timed-assertions verification

Last synced: 11 Jan 2026

https://github.com/ucsc-vama/essent

high-performance RTL simulator

chisel firrtl rtl scala

Last synced: 17 Jan 2026

https://github.com/fyralabs/chisel-operator

Kubernetes Operator for Chisel

chisel inlets inlets-pro inletsdev k8s k8s-operator kubernetes kubernetes-operator tunnel tunneling

Last synced: 11 Oct 2025

https://github.com/maltanar/fpga-tidbits

Chisel components for FPGA projects

chisel fpga hardware-libraries

Last synced: 07 Oct 2025

https://github.com/freechipsproject/diagrammer

Provides dot visualizations of chisel/firrtl circuits

chisel chisel3 firrtl visualization

Last synced: 17 Jan 2026

https://github.com/ovh/sv2chisel

(System)Verilog to Chisel translator

chisel eda transpiler verilog

Last synced: 08 Apr 2025

https://github.com/carlosedp/chiselv

A RISC-V Core (RV32I) written in Chisel HDL

chisel core fpga risc-v riscv

Last synced: 16 Aug 2025

https://github.com/ucb-bar/saturn-vectors

Chisel RISC-V Vector 1.0 Implementation

chisel cpu microarchitecture risc-v rvv vectors

Last synced: 07 Apr 2025

https://github.com/azumi67/direct_chisel

Establishing a Direct tunnel using chisel between Servers and Client - IPV4 | IPV6 - TCP | UDP - [5] Kharej [1] IRAN

chisel openvpn tcp tunnel udp v2ray wireguard

Last synced: 13 Jun 2025

https://github.com/FyraLabs/chisel-operator

Kubernetes Operator for Chisel

chisel inlets inlets-pro inletsdev k8s k8s-operator kubernetes kubernetes-operator tunnel tunneling

Last synced: 31 Mar 2025

https://github.com/sifive/chisel-circt

Library to compile Chisel circuits using LLVM/MLIR (CIRCT)

chisel circt mlir scala

Last synced: 22 Apr 2025

https://github.com/rhysd/riscv32-cpu-chisel

Learning how to make RISC-V 32bit CPU with Chisel

chisel chisel3 cpu risc-v

Last synced: 03 Sep 2025

https://github.com/luoqisheng/lldb-symbolic

lldb命令-symbolic

chisel custom-commend lldb

Last synced: 06 Apr 2025

https://github.com/thoughtworks/hardposit-chisel3

Chisel library for Unum Type-III Posit Arithmetic

chisel chisel3 firrtl floating-point fpu posit rtl scala unum verilog

Last synced: 02 Sep 2025

https://github.com/microdynamics-cpu/tree-core-cpu

:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

chisel cpu processor riscv rt-thread rtl scala softcore verilator

Last synced: 21 Jul 2025

https://github.com/IBM/perfect-chisel

Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program

chisel hdl rtl

Last synced: 22 Apr 2025

https://github.com/grebe/ofdm

Chisel Things for OFDM

chip-generator chisel chisel3 firrtl rtl scala verilog

Last synced: 18 Mar 2025

https://github.com/animmouse/socks5-proxy-codespaces

SOCKS5 proxy running on GitHub Codespaces using Chisel

chisel codespaces github-codespaces proxy socks socks5 socks5-proxy

Last synced: 26 Jul 2025

https://github.com/wangrunji0408/rjrouter

[AFK] Hardware router in Chisel (THU Network Joint Lab 2020)

chisel router

Last synced: 02 Jul 2025

https://github.com/maxxsoft/bossa

BOOM's Simulation Accelerator.

accelerator boom chipyard chisel firrtl risc-v riscv rocket rocket-chip rtl simulation soc verilator

Last synced: 22 Apr 2025

https://github.com/yasnakateb/cgras

Coarse Grained Reconfigurable Arrays with Chisel3

cgras chisel chisel-test chisel3 computer-architecture hardware sbt scala

Last synced: 05 Aug 2025

https://github.com/sifive/chisel-circt-demo

Demonstration of a project using sifive/chisel-circt

chisel circt mlir scala

Last synced: 25 Apr 2025

https://github.com/maxxsoft/frenda

Split large FIRRTL into separated modules for incremental compilation.

chisel compiler firrtl hardware incremental-compilation

Last synced: 22 Apr 2025

https://github.com/sinakarvandi/hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

asic asic-design chisel chisel3 fpga gtkwave modelsim netlist openlane openram verilator verilog vhdl vitis vitis-hls vivado vivado-hls

Last synced: 26 Oct 2025

https://github.com/carlosedp/chisel-template

Chisel HDL Template Repository

chisel fpga hardware hdl scala

Last synced: 19 Mar 2025

https://github.com/openxiangshan/chiselaia

RISC-V AIA in Chisel

aia chisel interrupt riscv

Last synced: 20 Jun 2025

https://github.com/csharpermantle/ics2023

ICS2023 PA & YSYX Workbench

chisel nju-ics riscv ysyx

Last synced: 01 Sep 2025

https://github.com/animmouse/socks5-proxy-actions

SOCKS5 proxy running on GitHub Actions using Chisel

actionshackathon21 chisel github-actions proxy socks socks5 socks5-proxy

Last synced: 19 Mar 2025

https://github.com/openxiangshan/openncb

Open-source Non-coherent CHI Bridge (CHI SN-F to AXI-4 bridge)

amba-axi amba-chi axi4 bus chisel chisel3 protocol-bridge soc

Last synced: 26 Jun 2025

https://github.com/atrosinenko/simpleinst

Make writing trivial inst{ruction,rumentation}s for RocketChip as simple as writing the C code

chisel ebpf instrumentation risc-v rocc rocketchip

Last synced: 14 Jun 2025

https://github.com/ltfschoen/mudtemplate

Build Ethereum DApps with MUD v2 in a Docker container

anvil cast chisel docker ethereum ethglobal23 forge foundry lattice mud vitejs

Last synced: 03 Aug 2025

https://github.com/serjzimmerman/tang-nano-9k-projects

Personal playground for learning Verilog and FPGAs

chisel fpga nix scala

Last synced: 07 May 2025

https://github.com/yasnakateb/chipyardintegration

😱 RoCC Accelerator Integration with Chipyard

accelerators chipyard chisel chisel3 computer-architecture hardware hardware-acceleration integration risc-v rocc rocket rocket-chip sbt scala simulation verilator

Last synced: 06 Feb 2026

https://github.com/buhe/study_fpga

💾 fpga study with open source tools (on macos)

chisel chisel3 fpga hardware tang-nano verilog

Last synced: 17 Oct 2025

https://github.com/rismicrodevices/openncb

Open-source Non-coherent CHI Bridge (CHI SN-F to AXI-4 bridge)

amba amba-axi amba-chi axi axi4 bus chi chisel chisel3 protocol-bridge protocol-converter soc soc-design

Last synced: 09 May 2025

https://github.com/justin-p/ansible-role-chisel

A Ansible role to deploy a https://github.com/jpillora/chisel client and/or server as a systemd service.

ansible ansible-galaxy ansible-role chisel golang hacktoberfest http systemd tcp tunnel

Last synced: 29 Oct 2025

https://github.com/ucb-bar/mada

Agile FPGA SoC design with Chisel and Mill.

chisel fpga millbuild

Last synced: 29 Jul 2025

https://github.com/r4um/sysdig-chisels

Misc sysdig chisels

chisel sysdig

Last synced: 15 Mar 2025

https://github.com/yasnakateb/chiselprocessor

Multicycle processor in Chisel3

chisel chisel3 computer-architecture cpu mips processor sbt scala

Last synced: 04 Oct 2025

https://github.com/sammck-go/wstunnel

wstunnel provides extensible, secure TCP tunneling through an HTTP/websocket server

chisel firewall port-forwarding proxy-server reverse-proxy ssh ssh-tunnel tcp-ip tunnel websocket

Last synced: 14 Jan 2026

https://github.com/rakshans1/wp-starter

Worpress theme starter with Chisel and Timber

chisel itcss timber wordpress wordpress-starter-theme

Last synced: 02 Apr 2025

https://github.com/xdtianyu/docker-auto-builds

Repo for docker hub auto builds

android arukas bluemix chisel docker gitlab-runner heroku openshift sshd

Last synced: 05 Jul 2025

https://github.com/yasnakateb/chiselnotes

Chisel3 examples

chisel chisel3 examples sbt scala

Last synced: 27 Dec 2025

https://github.com/64/rave32

An unpipelined 32-bit RISC-V CPU, written in Chisel.

chisel hardware risc-v rtl

Last synced: 02 Mar 2025

https://github.com/vitalyankh/open-fpga-tutorial

Open FPGA Tutorial

chisel fpga verilog

Last synced: 09 Feb 2026

https://github.com/carlosedp/chisel-bleep-template

A Chisel HDL template using Scala Bleep build tool

bleep chisel fpga hdl rtl scala

Last synced: 02 Apr 2025

https://github.com/forestfoxx/awesome-hardware-fuzzing

A curated list of research and repositories on the novel technique of hardware fuzzing

awesome awesome-list chisel cpu fuzzing fuzzing-paper hardware papers risc-v spinalhdl verification verilog x86

Last synced: 26 Jun 2025

https://github.com/proska/icfpt2016_design_competition

alpha-beta-pruning chisel chisel3 genetic-algorithm java monte-carlo-tree-search scala swift trax verilog-hdl

Last synced: 26 Jun 2025

https://github.com/edwardcwang/microdemo

Chisel RTL demo with blinking and interactivity. Use https://github.com/ucb-bar/chisel-template for a blank Chisel project template

chisel chisel3 demo rtl sample

Last synced: 31 Jul 2025

https://github.com/tgagor/docker-chiseled-corretto

Playing with Cannonicals Chisel tool, I was curious what benefits it could provide with Corretto

chisel corretto minimal

Last synced: 01 Feb 2026

https://github.com/nathsou/yodl

Yet anOther hardware Description Language

chisel circuit firrtl fpga hardware-description-language hdl verilog

Last synced: 05 Jan 2026

https://github.com/haouo/vriscv-cpu

5 Stage Pipeline CPU base on RV32I with a few V-Extension Support

chisel riscv

Last synced: 24 Dec 2025

https://github.com/mgnfy-view/foundry-ethernaut

Porting all Ethernaut challenges to Foundry

anvil chisel ethernaut-ctf forge foundry smart-contracts solidity solidity-hack

Last synced: 02 Mar 2025

https://github.com/bindless-chicken/chisel-blinky

Boilerplate for a full project with chisel and a DE0 Nano

chisel chisel3 de0-nano verilog

Last synced: 25 Jun 2025