https://github.com/chipsalliance/chisel

Chisel: A Modern Hardware Design Language

chip-generator chisel chisel3 firrtl rtl scala verilog

Last synced: 12 May 2025

https://github.com/SingularityKChen/dl_accelerator

Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions

chisel3 deep-learning-accelerator eyeriss final-year-project risc-v

Last synced: 22 Apr 2025

https://github.com/freechipsproject/diagrammer

Provides dot visualizations of chisel/firrtl circuits

chisel chisel3 firrtl visualization

Last synced: 17 Jan 2026

https://github.com/microdynamics-cpu/tree-core-ide

:deciduous_tree: The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

chisel3 ide processor riscv simualtion verilog vscode-extension waveform webgl

Last synced: 14 Mar 2025

https://github.com/agile-hw/lectures

Lectures for the Agile Hardware Design course in Jupyter Notebooks

agile-hardware chisel3 jupyter scala

Last synced: 22 Apr 2025

https://github.com/howardlau1999/yatcpu

Yet another toy CPU.

chisel-generator chisel3 cpu risc-v riscv

Last synced: 23 Jul 2025

https://github.com/rhysd/riscv32-cpu-chisel

Learning how to make RISC-V 32bit CPU with Chisel

chisel chisel3 cpu risc-v

Last synced: 03 Sep 2025

https://github.com/thoughtworks/hardposit-chisel3

Chisel library for Unum Type-III Posit Arithmetic

chisel chisel3 firrtl floating-point fpu posit rtl scala unum verilog

Last synced: 02 Sep 2025

https://github.com/jiegec/fpu-wrappers

Wrappers for open source FPU hardware implementations.

chisel3 fpu hdl spinalhdl

Last synced: 09 Feb 2026

https://github.com/grebe/ofdm

Chisel Things for OFDM

chip-generator chisel chisel3 firrtl rtl scala verilog

Last synced: 18 Mar 2025

https://github.com/ekiwi/pynq

PYNQ with Chisel and Rust

chisel3 dma pynq python rust

Last synced: 14 Jul 2025

https://github.com/merledu/caravan

A caravan equipped with API for creating bus protocols in Chisel with ease.

amba bus-protocols caravan chisel-generator chisel3 on-chip-network wishbone

Last synced: 22 Apr 2025

https://github.com/yasnakateb/cgras

Coarse Grained Reconfigurable Arrays with Chisel3

cgras chisel chisel-test chisel3 computer-architecture hardware sbt scala

Last synced: 05 Aug 2025

https://github.com/nhynes/chisel3-axi

Chisel3 AXI4-{Lite, Full, Stream} Definitions

axi4 chisel3 fpga hdl

Last synced: 27 Oct 2025

https://github.com/enkerewpo/methane

A polyphonic synthesizer built on fpga and esp32

chisel3 esp32 fpga music-hardware synthesizer systemverilog verilog

Last synced: 27 Apr 2025

https://github.com/codingplatelets/transformer_mm

Accelerator for LLM Based on Chisel3

chisel3 hardware-acceleration llm transformer verilog

Last synced: 17 Jul 2025

https://github.com/jiegec/fpnew-wrapper

A chisel3 wrapper for pulp-platform/fpnew

chisel3 fpu hardware-libraries

Last synced: 08 Jan 2026

https://github.com/origami404/minirv-chisel

2023 年学校 CPU 设计课程作业, 一个使用 Chisel 编写的简单 RV32I CPU 核心

chisel3 cpu hitsz homework

Last synced: 10 Apr 2025

https://github.com/sinakarvandi/hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

asic asic-design chisel chisel3 fpga gtkwave modelsim netlist openlane openram verilator verilog vhdl vitis vitis-hls vivado vivado-hls

Last synced: 26 Oct 2025

https://github.com/samadpls/aleph

Aleph is a single cycle processor that carries out one instruction in a single clock cycle

chisel3 risc-v riscv scala single-cycle-processor

Last synced: 27 Oct 2025

https://github.com/openxiangshan/openncb

Open-source Non-coherent CHI Bridge (CHI SN-F to AXI-4 bridge)

amba-axi amba-chi axi4 bus chisel chisel3 protocol-bridge soc

Last synced: 26 Jun 2025

https://github.com/atrosinenko/composite-video-generator

Example of composite video generation with Chisel (B/W for now)

chisel3 fpga scala

Last synced: 14 Jun 2025

https://github.com/buhe/study_fpga

💾 fpga study with open source tools (on macos)

chisel chisel3 fpga hardware tang-nano verilog

Last synced: 17 Oct 2025

https://github.com/rismicrodevices/openncb

Open-source Non-coherent CHI Bridge (CHI SN-F to AXI-4 bridge)

amba amba-axi amba-chi axi axi4 bus chi chisel chisel3 protocol-bridge protocol-converter soc soc-design

Last synced: 09 May 2025

https://github.com/yasnakateb/chipyardintegration

😱 RoCC Accelerator Integration with Chipyard

accelerators chipyard chisel chisel3 computer-architecture hardware hardware-acceleration integration risc-v rocc rocket rocket-chip sbt scala simulation verilator

Last synced: 06 Feb 2026

https://github.com/sinakarvandi/fpga

Random FPGA Projects

chisel3 fpga verilog vhdl vitis vivado zynq

Last synced: 24 Dec 2025

https://github.com/yasnakateb/chiselprocessor

Multicycle processor in Chisel3

chisel chisel3 computer-architecture cpu mips processor sbt scala

Last synced: 04 Oct 2025

https://github.com/suda-morris/suda_riscv

Playing with FPGA and RISC-V

chisel3 fpga risc-v verilog

Last synced: 27 Jan 2026

https://github.com/gogolb/riscy-adventure

chisel3 risc-processor risc-v riscv32 scala

Last synced: 07 Oct 2025

https://github.com/yasnakateb/chiselnotes

Chisel3 examples

chisel chisel3 examples sbt scala

Last synced: 27 Dec 2025

https://github.com/shiritai/aias-lab4-spring-2024

Lab4 of AI computing Architecture and System (2024 spring) around basic chisel design

adder booth-multiplier chisel3 scala

Last synced: 24 Mar 2025

https://github.com/niw/chisel_test

A simple Chisel test project for myself to learn Chisel and FPGA.

chisel3 fpga orangecrab scala tinyfpga verilog

Last synced: 20 Oct 2025

https://github.com/bindless-chicken/chisel-blinky

Boilerplate for a full project with chisel and a DE0 Nano

chisel chisel3 de0-nano verilog

Last synced: 25 Jun 2025

https://github.com/diohabara/chisel_riscv

RISC-V CPU Core

chisel3 cpu riscv

Last synced: 25 Mar 2025

https://github.com/proska/icfpt2016_design_competition

alpha-beta-pruning chisel chisel3 genetic-algorithm java monte-carlo-tree-search scala swift trax verilog-hdl

Last synced: 26 Jun 2025

https://github.com/yasnakateb/chisel7segment

BCD to 7 Segment Decoder in Chisel3

chisel-test chisel3 sbt scala seven-segment simple-project

Last synced: 19 Jul 2025

https://github.com/edwardcwang/microdemo

Chisel RTL demo with blinking and interactivity. Use https://github.com/ucb-bar/chisel-template for a blank Chisel project template

chisel chisel3 demo rtl sample

Last synced: 31 Jul 2025

https://github.com/shiritai/aias-lab5-spring-2024

Lab5 of AI computing Architecture and System (2024 spring) around advanced chisel design of FSM (e.g. `RobustCalculator`)

1a2b calculator chisel3 fsm hardware prng scala

Last synced: 24 Mar 2025