Ecosyste.ms: Awesome
An open API service indexing awesome lists of open source software.
https://github.com/pulp-platform/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
asic axi axi4 axi4-lite fpga hardware ip network-on-chip rtl systemverilog
Last synced: 30 Jul 2024
https://github.com/taichi-ishitani/tvip-axi
AMBA AXI VIP
amba amba-axi axi axi4 systemverilog uvm vip
Last synced: 30 Jul 2024
https://github.com/rggen/rggen
Code generation tool for configuration and status registers
amba apb asic axi csr eda fpga ral register-descriptions rtl soc systemverilog uvm uvm-ral-model uvm-register-model verilog vhdl wiki-documents wishbone-bus
Last synced: 30 Jul 2024
https://github.com/taichi-ishitani/tnoc
Network on Chip Implementation written in SytemVerilog
amba amba-axi axi axi4 network-on-chip noc systemverilog uvm
Last synced: 01 Aug 2024