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Projects in Awesome Lists tagged with register-descriptions
A curated list of projects in awesome lists tagged with register-descriptions .
https://github.com/rggen/rggen
Code generation tool for configuration and status registers
amba apb asic axi csr eda fpga ral register-descriptions rtl soc systemverilog uvm uvm-ral-model uvm-register-model verilog vhdl wiki-documents wishbone-bus
Last synced: 30 Jul 2024
https://github.com/SystemRDL/systemrdl-compiler
SystemRDL 2.0 language compiler front-end
asic csr design-automation eda fpga hardware-description-language register-description-language register-descriptions registers systemrdl systemrdl-compiler
Last synced: 03 Aug 2024
https://github.com/Juniper/open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
asic eda fpga jspec register-descriptions registers systemrdl systemrdl-compiler systemverilog uvm
Last synced: 03 Aug 2024
https://github.com/SystemRDL/PeakRDL
Control and status register code generator toolchain
amba apb asic axi command-line-tool csr eda fpga hardware-description-language register-descriptions registers systemrdl-compiler systemverilog uvm uvm-register-model verilog
Last synced: 02 Aug 2024