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Projects in Awesome Lists tagged with jspec

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https://github.com/Juniper/open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

asic eda fpga jspec register-descriptions registers systemrdl systemrdl-compiler systemverilog uvm

Last synced: 11 May 2025

https://github.com/juniper/open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

asic eda fpga jspec register-descriptions registers systemrdl systemrdl-compiler systemverilog uvm

Last synced: 27 Jan 2026