Projects in Awesome Lists tagged with uvm
A curated list of projects in awesome lists tagged with uvm .
https://github.com/cocotb/cocotb
cocotb: Python-based chip (RTL) verification
python test uvm verification verilog vhdl
Last synced: 12 May 2025
https://github.com/maximecb/uvm
Fun, portable, minimalistic virtual machine.
bytecode bytecode-interpreter compiler containerization emulation emulator interpreter jit-compiler permacomputing rust sandboxing uvm virtual-machine
Last synced: 09 Apr 2025
https://github.com/openhwgroup/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
risc-v systemverilog uvm verification
Last synced: 15 May 2025
https://github.com/chipsalliance/surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
antlr antlr4-grammar elaboration linter parser parser-ast preprocessor python-api systemverilog uvm verilog vpi vpi-api vpi-standard
Last synced: 15 May 2025
https://github.com/chipsalliance/Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
antlr antlr4-grammar elaboration linter parser parser-ast preprocessor python-api systemverilog uvm verilog vpi vpi-api vpi-standard
Last synced: 21 Apr 2025
https://github.com/taichi-ishitani/tvip-axi
AMBA AXI VIP
amba amba-axi axi axi4 systemverilog uvm vip
Last synced: 23 Feb 2026
https://github.com/tymonx/logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
asic cmake cpp fpga hdl modelsim quartus rtl systemc systemverilog testing-rtl unit-tests uvm verification verilator verilog vivado xilinx
Last synced: 14 Apr 2025
https://github.com/rggen/rggen
Code generation tool for configuration and status registers
amba apb asic axi csr eda fpga ral register-descriptions rtl soc systemverilog uvm uvm-ral-model uvm-register-model verilog vhdl wiki-documents wishbone-bus
Last synced: 07 Jan 2026
https://github.com/nic30/hwt
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
codegen codegenerator compiler fpga hcl hls rtl simulator systemc systemverilog uvm verilog vhdl
Last synced: 08 Apr 2025
https://github.com/Nic30/hwt
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
codegen codegenerator compiler fpga hcl hls rtl simulator systemc systemverilog uvm verilog vhdl
Last synced: 15 Mar 2025
https://github.com/Juniper/open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
asic eda fpga jspec register-descriptions registers systemrdl systemrdl-compiler systemverilog uvm
Last synced: 11 May 2025
https://github.com/juniper/open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
asic eda fpga jspec register-descriptions registers systemrdl systemrdl-compiler systemverilog uvm
Last synced: 27 Jan 2026
https://github.com/taichi-ishitani/tnoc
Network on Chip Implementation written in SytemVerilog
amba amba-axi axi axi4 network-on-chip noc systemverilog uvm
Last synced: 08 Jan 2026
https://github.com/SystemRDL/PeakRDL
Control and status register code generator toolchain
amba apb asic axi command-line-tool csr eda fpga hardware-description-language register-descriptions registers systemrdl-compiler systemverilog uvm uvm-register-model verilog
Last synced: 22 Apr 2025
https://github.com/postmanlabs/uvm
Universal Virtual Machine for Node and Browser
Last synced: 16 May 2025
https://github.com/Shehab-Naga/ddr5_phy
DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
Last synced: 11 May 2025
https://github.com/kaushalmodi/custom_uvm_report_server
Customized UVM Report Server
cadence synopsys systemverilog uvm vcs xcelium
Last synced: 10 Mar 2026
https://github.com/taichi-ishitani/tvip-apb
Verification IP for AMBA APB Protocol
amba apb systemverilog uvm vip
Last synced: 17 Feb 2026
https://github.com/kumarrishav14/AXI
VIP for AXI Protocol
amba-axi asic-verification design-verification sv uvm
Last synced: 21 Nov 2025
https://github.com/ghonimo/pre_silicon-ahb-to_apb-verification
Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
ahb2apb digital-design questasim semiconductor simulation systemverilog testbench uvm uvm-verification verification verification-methodologies vip
Last synced: 02 Mar 2026
https://github.com/yuravg/uvm_tb_cross_bar
SystemVerilog UVM testbench example
systemverilog uvm verification
Last synced: 05 Mar 2026
https://github.com/rggen/rggen-sample-testbench
systemverilog uvm uvm-ral-model uvm-register-model verilog vhdl
Last synced: 05 Feb 2026
https://github.com/semify-eda/go.debug
Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster
eda hdl systemverilog testbench uvm verification verilator verilog
Last synced: 09 Apr 2026
https://github.com/ghonimo/formal-verification-of-an-ahb2apb-bridge
Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation including a final report and project progression presentation.
abp ahb ahb2 amba assertion-based-verification computer-ar formal-verification harward uvm verification
Last synced: 28 Feb 2026
https://github.com/sleekpanther/gpa-calculator
A GPA calculator in JavaFX attempting to use the Model View Controller (MVC) pattern
college event-handling fxml gpa grade jar java javafx javafx-application javafx-desktop-apps model-view-controller mvc noah noah-patullo noahpatullo pattullo pattulo patullo patulo uvm
Last synced: 10 Apr 2025
https://github.com/risto97/pygears-uvm
SystemC UVM environment generator for PyGears components. RTL simulated with Verilator
pygears systemc systemc-uvm-generator uvm verification verilator
Last synced: 10 Oct 2025
https://github.com/sleekpanther/uvm-blackboard-autofill-netid
Autofill NetID when logging into Blackboard & syncs across signed-in Chrome browsers
autofill blackboard chrome chrome-extension chrome-extensions google-chrome google-chrome-extension netid noah noah-patullo noahpatullo pattullo pattulo patullo patulo save-netid university-of-vermont username uvm
Last synced: 02 May 2026
https://github.com/pirate-emperor/cipherx
CipherX is a verification project for Advanced Encryption Standard (AES-128) using Universal Verification Methodology (UVM). It leverages Verilog, SystemVerilog, and Python to ensure robust encryption algorithm validation, integrating comprehensive UVM components and tests.
aes-128 cryptography cryptography-algorithms dataencryption dataencryptionstandards digitaldesign encrytption hardwareverification python security testing-framework uvm verification verilog
Last synced: 26 Jan 2026
https://github.com/sleekpanther/noah-patullo-repositories
A list of projects I've worked on. GitHub's organization is lacking in my opinion, so this serves as an index & root of all my work (I'm Noah Patullo, not Pattullo or Patulo. I have a unique name & this should help clarify who I am)
algorithm algorithm-design cpp cv game java linkedin noah noah-patullo noahpatullo pattullo pattulo patullo patulo portfolio python resume uvm
Last synced: 19 Apr 2026
https://github.com/thomasafroo/uvm-based-verification-of-4-bit-adder
A combinational adder project that contains verification in UVM.
Last synced: 06 Feb 2026
