Ecosyste.ms: Awesome
An open API service indexing awesome lists of open source software.
Projects in Awesome Lists by openhwgroup
A curated list of projects in awesome lists by openhwgroup .
https://github.com/openhwgroup/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
ariane asic cpu fpga risc-v rv64gc systemverilog-hdl
Last synced: 30 Jul 2024
https://github.com/openhwgroup/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Last synced: 31 Jul 2024
https://github.com/openhwgroup/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
risc-v systemverilog uvm verification
Last synced: 01 Aug 2024
https://github.com/openhwgroup/cvfpu
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
Last synced: 02 Aug 2024
https://github.com/openhwgroup/force-riscv
Instruction Set Generator initially contributed by Futurewei
Last synced: 02 Aug 2024
https://github.com/openhwgroup/cvw
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
Last synced: 01 Aug 2024
https://github.com/openhwgroup/cv32e40x
4 stage, in-order, compute RISC-V core based on the CV32E40P
Last synced: 02 Aug 2024
https://github.com/openhwgroup/programs
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
Last synced: 04 Aug 2024
https://github.com/openhwgroup/cv32e40s
4 stage, in-order, secure RISC-V core based on the CV32E40P
Last synced: 03 Aug 2024
https://github.com/openhwgroup/core-v-xif
RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
Last synced: 02 Aug 2024
https://github.com/openhwgroup/cv-hpdcache
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
Last synced: 02 Aug 2024
https://github.com/openhwgroup/cv32e41p
4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
Last synced: 02 Aug 2024
https://github.com/openhwgroup/cve2
The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
Last synced: 03 Aug 2024
https://github.com/openhwgroup/riscv_vm
Instructions to import Ubuntu guest Virtual Machine for RISC-V development for the VEGA board
Last synced: 30 Jul 2024