Ecosyste.ms: Awesome
An open API service indexing awesome lists of open source software.
https://github.com/ZipCPU/zipcpu
A small, light weight, RISC CPU soft core
cpu cross-compiler fpga risc-cpu soft-core verilator verilog wishbone wishbone-bus zipcpu
Last synced: 30 Jul 2024
https://github.com/ZipCPU/wbuart32
A simple, basic, formally verified UART controller
fpga serialport uart uart-verilog verilator verilog wishbone wishbone-bus
Last synced: 30 Jul 2024
https://github.com/rggen/rggen
Code generation tool for configuration and status registers
amba apb asic axi csr eda fpga ral register-descriptions rtl soc systemverilog uvm uvm-ral-model uvm-register-model verilog vhdl wiki-documents wishbone-bus
Last synced: 30 Jul 2024
