Projects in Awesome Lists tagged with uart-verilog
A curated list of projects in awesome lists tagged with uart-verilog .
https://github.com/pconst/basic_verilog
Must-have verilog systemverilog modules
altera debounce delay encoder fifo fpga hls pwm spi-interface spi-master synchronizer tcl uart uart-controller uart-protocol uart-receiver uart-tx uart-verilog verilog xilinx
Last synced: 26 Mar 2025
https://github.com/pConst/basic_verilog
Must-have verilog systemverilog modules
altera debounce delay encoder fifo fpga hls pwm spi-interface spi-master synchronizer tcl uart uart-controller uart-protocol uart-receiver uart-tx uart-verilog verilog xilinx
Last synced: 14 Mar 2025
https://github.com/ZipCPU/wbuart32
A simple, basic, formally verified UART controller
fpga serialport uart uart-verilog verilator verilog wishbone wishbone-bus
Last synced: 14 Mar 2025
https://github.com/ben-marshall/uart
A simple implementation of a UART modem in Verilog.
fpga hardware uart uart-verilog verilog verilog-hdl
Last synced: 22 Mar 2025
https://github.com/addisonelliott/logifindfpgatest
This is a Quartus Prime FPGA project testing the functionality of the LogiFind Altera Cyclone IV EP4CE6E22C8N Development Board. This product can also be found on eBay where I bought it from. I hope to provide base code that will help others in their learning with this development board.
7-segment altera buzzer cyclone-iv easyfpga ep4ce6e22c8n fpga ir-receiver logifind nec-verilog pl2303 quartus-prime uart-verilog verilog verilog-hdl
Last synced: 28 Mar 2025
https://github.com/yasnakateb/uartcommunication
☎️ UART Communication Implementation in Verilog HDL
icarus-verilog iverilog serial-communication uart uart-interface uart-protocol uart-verilog verilog
Last synced: 13 Mar 2025
https://github.com/wissance/quickrs232
A versatile full-duplex RS232 FPGA module with internal FIFO buffer on RX
altera-uart fpga fpga-programming fpga-rs232 rs232 serial-communication serial-communication-fpga uart uart-verilog verilog-library verilog-rs232 verilog-serial-port verilog-uart
Last synced: 04 Apr 2025
https://github.com/mengstr/vuart
WIP - Smallish UART written in Verilog
uart uart-verilog verilog wip-do-not-use
Last synced: 25 Feb 2025
https://github.com/tahirzia-1/uart-transmitter-and-receiver
A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.
fpga-board fpga-programming fpga-soc nexys4ddr rtl simulation systemverilog testbench uart uart-receiver uart-transmitter uart-verilog verilog verilog-hdl verilog-project vivado vivado-hls vivado-simulator
Last synced: 04 Mar 2025
