Projects in Awesome Lists tagged with icarus-verilog
A curated list of projects in awesome lists tagged with icarus-verilog .
https://github.com/olofk/edalize
An abstraction library for interfacing EDA tools
altera eda fossi fpga ghdl icarus-verilog icestorm lattice modelsim riviera-pro simulation spyglass synthesis systemverilog verilator verilog vhdl vivado xilinx yosys
Last synced: 14 May 2025
https://github.com/mshr-h/vscode-verilog-hdl-support
HDL support for VS Code
bluespec-systemverilog ctags hacktoberfest icarus-verilog iverilog language-server-client modelsim svls systemverilog systemverilog-support verilator verilog verilog-hdl vivado vscode
Last synced: 08 Apr 2025
https://github.com/dpretet/async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
asic asic-design async cdc cross-clock-domain fifo fifo-cache fifo-queue fpga hdl icarus-verilog synthesis verification verilator verilog verilog-hdl
Last synced: 22 Apr 2025
https://github.com/stnolting/neorv32-verilog
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
asic fpga ghdl icarus-verilog neorv32 verilog
Last synced: 14 May 2025
https://github.com/unixb0y/systemverilogsha256
SHA256 in (System-) Verilog / Open Source FPGA Miner
bitcoin fpga icarus-verilog mining sha256 systemverilog verilog
Last synced: 15 Apr 2025
https://github.com/dpretet/svut
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
flow foss gtkwave icarus-verilog mit-license python simulation simulator surfer svut systemverilog tdd tdd-utilities testcase vcd verification-methodologies verilator verilog
Last synced: 22 Apr 2025
https://github.com/sgherbst/svreal
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
fixed-point floating-point icarus icarus-verilog irun iverilog ncsim simulation synthesis synthesizable systemverilog vcs verilator verilog vivado xcelium xrun
Last synced: 11 May 2025
https://github.com/yasnakateb/pipelinedarm
💎 A 32-bit ARM Processor Implementation in Verilog HDL
arm arm-pipeline arm-processor cpu icarus-verilog iverilog verilog verilog-hdl
Last synced: 13 Mar 2025
https://github.com/aditeyabaral/ddco-lab-ue18cs207
A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.
computer-organization digital-design icarus-verilog logic-programming verilog verilog-code
Last synced: 09 Mar 2025
https://github.com/Elphel/vdt-plugin
mirror of https://git.elphel.com/Elphel/vdt-plugin
cocotb eclipse eclipse-plugin gtkwave icarus-verilog ide quartus verilog vivado
Last synced: 29 Nov 2024
https://github.com/addisonelliott/scic
Project of Addison Elliott and Dan Ashbaugh to create IC layout of 32-bit custom CPU used in teaching digital design at SIUE.
asic cadence cpu digital gate icarus-verilog rtl simulation synthesis tcl verilog
Last synced: 28 Mar 2025
https://github.com/theonekevin/icarusext
iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.
gtkwave icarus-verilog verilog verilog-testbenches vscode-extension
Last synced: 22 Apr 2025
https://github.com/yasnakateb/nocrouter
👶🏻 My first baby steps into the world of NoC
icarus-verilog iverilog router verilog verilog-hdl
Last synced: 13 Mar 2025
https://github.com/yasnakateb/pipelinedmips
🔮 A 16-bit MIPS Processor Implementation in Verilog HDL
cpu icarus-verilog iverilog mips mips-pipeline mips-processor pipeline verilog verilog-hdl
Last synced: 17 Jun 2025
https://github.com/yasnakateb/wmcontroller
✨🐾✨ A Control System for Washing Machine in Verilog HDL
icarus-verilog washing-machine
Last synced: 13 Mar 2025
https://github.com/aditeyabaral/up-down-counter
A simple up-down counter made using icarus verilog as a part of the Digital Design and Computer Organization course (UE18CS201) at PES University.
counter digital-design icarus-verilog logic-programming verilog verilog-project
Last synced: 09 Mar 2025
https://github.com/yasnakateb/aes
🔐 Hardware Implementation Of AES Algorithm in Verilog HDL
aes aes-128 aes-encryption encryption encryption-algorithm icarus-verilog iverilog verilog verilog-hdl
Last synced: 13 Mar 2025
https://github.com/yasnakateb/fifomemory
📍 A FIFO Memory Implementation in Verilog HDL
Last synced: 13 Mar 2025
https://github.com/yasnakateb/uartcommunication
☎️ UART Communication Implementation in Verilog HDL
icarus-verilog iverilog serial-communication uart uart-interface uart-protocol uart-verilog verilog
Last synced: 13 Mar 2025
https://github.com/quentinwach/computer-engineering
📝 Notes on computer engineering. From application to custom computer design.
book computer-architecture course cpu cpu-architecture documentation gtkwave hack hack-computer icarus icarus-verilog iverilog logisim nand2tetris nand2tetris-assignments nand2tetris-projects nand2tetris-solutions recources verilog
Last synced: 14 Jun 2025
https://github.com/yasnakateb/trafficlightcontroller
🚦 A digital controller to control traffic in Verilog HDL
icarus-verilog traffic-light-controller
Last synced: 13 Mar 2025
https://github.com/stnolting/icarus-verilog-prebuilt
📦 Prebuilt Icarus Verilog simulator package for x64 Linux.
asic fpga hdl icarus-verilog linux prebuilt-binaries simulator verilog
Last synced: 14 May 2025
https://github.com/yasnakateb/sdramcontroller
🛠 A SDRAM controller in Verilog HDL
icarus-verilog iverilog memory-controller sdram sdram-controller verilog verilog-hdl
Last synced: 13 Mar 2025
https://github.com/melchisedech333/verilog-experiments
:space_invader: My studies with Verilog and notions of digital systems.
digital-system-design digital-systems digital-systems-design digital-systems-fundamentals hdl icarus-verilog verilog verilog-code verilog-examples verilog-hdl verilog-project
Last synced: 29 Mar 2025
https://github.com/dvvcz/cpe-133
icarus-verilog iverilog systemverilog verilog vivado
Last synced: 23 Feb 2025
https://github.com/vballoli/mips-processor
Un-pipelined partial MIPS processor implementation in Verilog
Last synced: 25 Mar 2025
https://github.com/fuwn/iverilog-test-bench
☀️ Icarus Verilog Test-bench Template
Last synced: 30 Mar 2025
https://github.com/lucanmudkip20/eda
EDA (Exploratory Data Analysis) is a crucial step in data science where analysts investigate data sets to summarize their main characteristics. It involves using visualizations and statistical techniques to understand the data and uncover patterns, trends, and relationships within it.
c classification data-visualization icarus-verilog keras lattice nlp position pytorch qt rnn text-classification vhdl xilinx
Last synced: 19 Feb 2025
https://github.com/richasavant/icarus-verilog-hdl-logical-circuits-2023
This repository focuses on designing and simulating logical circuits using Verilog HDL (Hardware Description Language) with the Icarus Verilog simulator.
adders arithmetic-circuits combinational-circuit decoders demultiplexer encoders flip-flops hdl icarus-verilog logic-gates multiplexer ripple-carry-adder sequential-circuits shift-registers
Last synced: 04 Mar 2025
