Ecosyste.ms: Awesome
An open API service indexing awesome lists of open source software.
Projects in Awesome Lists tagged with yosys
A curated list of projects in awesome lists tagged with yosys .
https://github.com/the-openroad-project/openlane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
130nm asic caravel foundry klayout magic netgen openram openroad rtl rtl2gds skywater soc-design system-on-chip verilog vlsi yosys
Last synced: 30 Sep 2024
https://github.com/The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
130nm asic caravel foundry klayout magic netgen openram openroad rtl rtl2gds skywater soc-design system-on-chip verilog vlsi yosys
Last synced: 02 Aug 2024
https://github.com/m-labs/nmigen
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
Last synced: 02 Aug 2024
https://github.com/olofk/edalize
An abstraction library for interfacing EDA tools
altera eda fossi fpga ghdl icarus-verilog icestorm lattice modelsim riviera-pro simulation spyglass synthesis systemverilog verilator verilog vhdl vivado xilinx yosys
Last synced: 02 Aug 2024
https://github.com/nturley/netlistsvg
draws an SVG schematic from a JSON netlist
diagram elk klayjs netlist visualization yosys
Last synced: 30 Jul 2024
https://github.com/zachjs/sv2v
SystemVerilog to Verilog conversion
conversion systemverilog verilog yosys
Last synced: 30 Jul 2024
https://github.com/chipsalliance/fpga-tool-perf
FPGA tool performance profiling
arachne-pnr conda-environment f4pga fpga nextpnr perf performance-analysis symbiflow toolchain vpr yosys
Last synced: 03 Aug 2024
https://github.com/YoWASP/yosys
Unofficial Yosys WebAssembly packages
fpga pypi python webassembly yosys yowasp
Last synced: 09 Aug 2024
https://github.com/SymbiFlow/sphinxcontrib-hdl-diagrams
Sphinx Extension which generates various types of diagrams from Verilog code.
diagrams documentation documentation-tool fpga hdl rtl sphinx sphinx-extension symbiflow verilog yosys
Last synced: 03 Aug 2024
https://github.com/kivikakk/hdx
[mirror] HDL development environment on Nix.
amaranth-hdl fpga hdl nextpnr nix yosys
Last synced: 04 Aug 2024
https://github.com/kittennbfive/5A-75B-tools
a collection of tools made while messing with the Colorlight 5A-75B V7.0 and some notes using ECP5 with Yosys
5a-75b chubby75 colorlight ecp5 fpga nextpnr nextpnr-ecp5 verilog yosys
Last synced: 02 Aug 2024
https://github.com/alangarf/tm1638-verilog
A basic verilog driver for the TM1638 LED and key matrix chip
arachne-pnr ice40 icestorm tm1638 verilog yosys
Last synced: 06 Aug 2024
https://github.com/freand76/digsim
An interactive digital logic simulator with verilog support (Yosys)
logic python rtl simulation simulator vcd verilog yosys
Last synced: 03 Aug 2024
