Projects in Awesome Lists tagged with vlsi

https://github.com/the-openroad-project/openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

130nm asic caravel foundry klayout magic netgen openram openroad rtl rtl2gds skywater soc-design system-on-chip verilog vlsi yosys

Last synced: 30 Sep 2024

https://github.com/The-OpenROAD-Project/OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

130nm asic caravel foundry klayout magic netgen openram openroad rtl rtl2gds skywater soc-design system-on-chip verilog vlsi yosys

Last synced: 02 Aug 2024

https://github.com/limbo018/DREAMPlace

Deep learning toolkit-enabled VLSI placement

deep-learning gpu-acceleration pytorch vlsi vlsi-physical-design vlsi-placement

Last synced: 03 Aug 2024

https://github.com/VLSI-EDA/PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

altera asic fpga hardware-designs hardware-libraries hardware-modules lattice osvvm poc-library python regression-testing simulation synthesis testbenches uvvm verification vhdl vlsi vunit xilinx

Last synced: 02 Aug 2024

https://github.com/OpenTimer/OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

cad circuit-analysis circuit-simulation circuit-simulator computer-aided-design cpp17 eda electronic-design-automation parallel-computing sta static-timing-analysis verilog vlsi vlsi-circuits vlsi-physical-design

Last synced: 30 Jul 2024

https://github.com/DegateCommunity/Degate

A modern and open-source cross-platform software for chips reverse engineering.

chips cpp cross-platform cybersecurity gui multi-platform reverse-engineering security security-tools verilog vhdl vlsi

Last synced: 03 Aug 2024

https://github.com/efabless/openlane2

The next generation of OpenLane, rewritten from scratch with a modular architecture

asic drc eda flow flows gdsii gf180mcu lvs openlane openroad pdk pnr rtl-to-gds silicon sky130 sta verilog vlsi

Last synced: 09 Aug 2024

https://github.com/AUCOHL/DFFRAM

Standard Cell Library based Memory Compiler using FF/Latch cells

asic-design electronics-design verilog vlsi vlsi-circuits vlsi-physical-design

Last synced: 03 Aug 2024

https://github.com/antonblanchard/vlsiffra

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

adder amaranth-hdl booth dadda multiplier physical-design verilog vlsi

Last synced: 01 Aug 2024

https://github.com/asyncvlsi/act

ACT hardware description language and core tools.

asynchronous-circuits asynchronous-vlsi cad chp circuit-simulator communicating-hardware-processes dataflow dataflow-programming design-automation eda hardware-description-language hdl language production-rules prs vlsi vlsi-cad

Last synced: 30 Jul 2024

https://github.com/danchitnis/EEsim

A browser-based SPICE circuit simulator

circuit cmos electronics emscripten ngspice simulation spice vlsi wasm webassembly webgl-plot

Last synced: 03 Aug 2024

https://github.com/ahmed-agiza/EDAViewer

EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!

cgo def def-viewer digitaldesign eda electronic-design-automation hardware hardware-design layout lef opendb opendb-database physical-synthesis pixijs server-side-rendering serverless serverless-side-rendering viewer vlsi webgl

Last synced: 03 Aug 2024

https://github.com/OpenTimer/Parser-SPEF

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

circuits computer-aided-design cpp17 eda electronic-design-automation parasitic spef sta static-timing-analysis vlsi vlsi-circuits vlsi-physical-design

Last synced: 30 Jul 2024

https://github.com/asyncvlsi/AMC

AMC: Asynchronous Memory Compiler

asynchronous-sram asynchronous-vlsi design-automation eda vlsi

Last synced: 30 Jul 2024

https://github.com/ahirsharan/32-Bit-Floating-Point-Adder

Verilog Implementation of 32-bit Floating Point Adder

verilog vlsi xilinx

Last synced: 02 Aug 2024

https://github.com/YosysHQ/padring

A padring generator for ASICs

asic chip eda vlsi yosys

Last synced: 03 Aug 2024

https://github.com/the-pinbo/robdd

A binary decision diagram is a directed acyclic graph used to represent a Boolean function. The ROBDD is a canonical form, which means that given an identical ordering of input variables, equivalent Boolean functions will always reduce to the same ROBDD.

bdd bdds boolean-algebra graphviz-dot ipynb-jupyter-notebook pthon3 robdd vlsi vlsi-cad

Last synced: 27 Sep 2024

https://codeberg.org/librecell/lctime

Characterization tool for CMOS digital standard-cells.

asic characterization chip cmos liberty ndlm ngspice python spice standard-cell timing vlsi

Last synced: 03 Aug 2024

https://codeberg.org/librecell/lclayout

Layout generator for CMOS standard-cells.

asic cmos digital generator layout standard-cell vlsi

Last synced: 03 Aug 2024