Ecosyste.ms: Awesome
An open API service indexing awesome lists of open source software.
Projects in Awesome Lists tagged with vlsi-circuits
A curated list of projects in awesome lists tagged with vlsi-circuits .
https://github.com/OpenTimer/OpenTimer
A High-performance Timing Analysis Tool for VLSI Systems
cad circuit-analysis circuit-simulation circuit-simulator computer-aided-design cpp17 eda electronic-design-automation parallel-computing sta static-timing-analysis verilog vlsi vlsi-circuits vlsi-physical-design
Last synced: 30 Jul 2024
https://github.com/AUCOHL/DFFRAM
Standard Cell Library based Memory Compiler using FF/Latch cells
asic-design electronics-design verilog vlsi vlsi-circuits vlsi-physical-design
Last synced: 03 Aug 2024
https://github.com/OpenTimer/Parser-Verilog
A Standalone Structural Verilog Parser
bison-yacc circuit computer-aided-design cpp17 eda electronic-design-automation flex verilog vlsi-circuits vlsi-physical-design
Last synced: 09 Aug 2024
https://github.com/OpenTimer/Parser-SPEF
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
circuits computer-aided-design cpp17 eda electronic-design-automation parasitic spef sta static-timing-analysis vlsi vlsi-circuits vlsi-physical-design
Last synced: 30 Jul 2024