Ecosyste.ms: Awesome
An open API service indexing awesome lists of open source software.
https://github.com/purdue-onchip/gds2Para
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
eda electronic-design-automation gdsii integrated-circuits interconnect parse spef vlsi vlsi-circuits
Last synced: 29 May 2024
![](https://github.com/purdue-onchip.png)
https://github.com/OpenTimer/Parser-SPEF
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
circuits computer-aided-design cpp17 eda electronic-design-automation parasitic spef sta static-timing-analysis vlsi vlsi-circuits vlsi-physical-design
Last synced: 29 May 2024
![](https://github.com/OpenTimer.png)
https://github.com/OpenTimer/OpenTimer
A High-performance Timing Analysis Tool for VLSI Systems
cad circuit-analysis circuit-simulation circuit-simulator computer-aided-design cpp17 eda electronic-design-automation parallel-computing sta static-timing-analysis verilog vlsi vlsi-circuits vlsi-physical-design
Last synced: 07 May 2024
![](https://github.com/OpenTimer.png)
https://github.com/ahmed-agiza/EDAViewer
EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
cgo def def-viewer digitaldesign eda electronic-design-automation hardware hardware-design layout lef opendb opendb-database physical-synthesis pixijs server-side-rendering serverless serverless-side-rendering viewer vlsi webgl
Last synced: 25 Apr 2024
![](https://github.com/ahmed-agiza.png)
https://byuccl.github.io/spydrnet/
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
cad circuit circuit-analysis circuit-design circuits computer-aided-design digital eda edif electronic-design-automation fpga fpgas hardware hardware-designs netlist netlist-parser netlists transformation transformations
Last synced: 17 Apr 2024
![](https://github.com/byuccl.png)
https://github.com/OpenTimer/Parser-Verilog
A Standalone Structural Verilog Parser
bison-yacc circuit computer-aided-design cpp17 eda electronic-design-automation flex verilog vlsi-circuits vlsi-physical-design
Last synced: 12 Apr 2024
![](https://github.com/OpenTimer.png)
https://github.com/byuccl/spydrnet
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
cad circuit circuit-analysis circuit-design circuits computer-aided-design digital eda edif electronic-design-automation fpga fpgas hardware hardware-designs netlist netlist-parser netlists transformation transformations
Last synced: 21 Mar 2024
![](https://github.com/byuccl.png)