https://github.com/OpenTimer/OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

cad circuit-analysis circuit-simulation circuit-simulator computer-aided-design cpp17 eda electronic-design-automation parallel-computing sta static-timing-analysis verilog vlsi vlsi-circuits vlsi-physical-design

Last synced: 14 Mar 2025

https://github.com/clin99/awesome-eda

circuit eda fpga gds lithography logic-synthesis open-source parser placement routing simulation static-timing-analysis systemverilog timer verification verilog

Last synced: 04 Jan 2026

https://github.com/OpenTimer/Parser-SPEF

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

circuits computer-aided-design cpp17 eda electronic-design-automation parasitic spef sta static-timing-analysis vlsi vlsi-circuits vlsi-physical-design

Last synced: 14 Mar 2025

https://github.com/malaksadek/statictiminganalyzer

A Logic Circuit Static Timing Analyzer Implemented in Python 🔌 ⚡ (2018)

c graph-algorithms html json logic-circuit logic-gates python scl static-timing-analysis verilog verilog-hdl

Last synced: 26 Feb 2026

https://github.com/crepopcorn/sta_check_temporary

This project is the script for STA report violated path checks temporarily (not final version due to confidentiality).

bash bash-script c checking linux perl python shell static-timing-analysis testing

Last synced: 12 Apr 2026