Projects in Awesome Lists by OpenTimer
A curated list of projects in awesome lists by OpenTimer .
https://github.com/OpenTimer/OpenTimer
A High-performance Timing Analysis Tool for VLSI Systems
cad circuit-analysis circuit-simulation circuit-simulator computer-aided-design cpp17 eda electronic-design-automation parallel-computing sta static-timing-analysis verilog vlsi vlsi-circuits vlsi-physical-design
Last synced: 14 Mar 2025
https://github.com/OpenTimer/Parser-Verilog
A Standalone Structural Verilog Parser
bison-yacc circuit computer-aided-design cpp17 eda electronic-design-automation flex verilog vlsi-circuits vlsi-physical-design
Last synced: 22 Jul 2025
https://github.com/OpenTimer/Parser-SPEF
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
circuits computer-aided-design cpp17 eda electronic-design-automation parasitic spef sta static-timing-analysis vlsi vlsi-circuits vlsi-physical-design
Last synced: 14 Mar 2025