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Projects in Awesome Lists tagged with openram

A curated list of projects in awesome lists tagged with openram .

https://github.com/google/skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

asic asic-library eda magic openram openroad pdk skywater

Last synced: 13 May 2025

https://github.com/the-openroad-project/openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

130nm asic caravel foundry klayout magic netgen openram openroad rtl rtl2gds skywater soc-design system-on-chip verilog vlsi yosys

Last synced: 14 May 2025

https://github.com/The-OpenROAD-Project/OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

130nm asic caravel foundry klayout magic netgen openram openroad rtl rtl2gds skywater soc-design system-on-chip verilog vlsi yosys

Last synced: 22 Apr 2025

https://github.com/efabless/caravel

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

caravel magic openram openroad picorv32 sky130 vexriscv yosys

Last synced: 17 Jan 2026

https://github.com/efabless/caravel_mpw-one

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

caravel magic openram openroad picorv32 sky130 yosys

Last synced: 17 Jan 2026

https://github.com/sinakarvandi/hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

asic asic-design chisel chisel3 fpga gtkwave modelsim netlist openlane openram verilator verilog vhdl vitis vitis-hls vivado vivado-hls

Last synced: 25 Feb 2026