Projects in Awesome Lists tagged with modelsim

https://github.com/olofk/edalize

An abstraction library for interfacing EDA tools

altera eda fossi fpga ghdl icarus-verilog icestorm lattice modelsim riviera-pro simulation spyglass synthesis systemverilog verilator verilog vhdl vivado xilinx yosys

Last synced: 14 May 2025

https://github.com/mshr-h/vscode-verilog-hdl-support

HDL support for VS Code

bluespec-systemverilog ctags hacktoberfest icarus-verilog iverilog language-server-client modelsim svls systemverilog systemverilog-support verilator verilog verilog-hdl vivado vscode

Last synced: 08 Apr 2025

https://github.com/tymonx/logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

asic cmake cpp fpga hdl modelsim quartus rtl systemc systemverilog testing-rtl unit-tests uvm verification verilator verilog vivado xilinx

Last synced: 14 Apr 2025

https://github.com/paebbels/json-for-vhdl

A JSON library implemented in VHDL.

fileformat fpga ghdl json lattice modelsim parser questasim simulation synthesis vhdl xilinx

Last synced: 29 Jul 2025

https://github.com/MJoergen/HyperRAM

Portable HyperRAM controller

altera artix avalon fpga hyperram intel lattice modelsim quartus questa questasim vhdl vivado xilinx

Last synced: 22 Apr 2025

https://github.com/cclienti/wavedisp

Python classes to create agnostic wave files for HDL simulator viewer

gtkwave modelsim python rivierapro vcd verilog vhdl

Last synced: 08 Apr 2026

https://github.com/itzzinfinity/100-days-of-rtl

Trying to get a new skill

altera digital electronics gowin modelsim quartus-prime rtl testbench verilog vivado xilinx xilinx-vivado

Last synced: 24 Jan 2026

https://github.com/paebbels/pyipcmi

A Python-based IP Core Management Infrastructure.

altera database infrastructure intel ip-core modelsim python3 quartus-prime questasim riviera-pro simulation synthesis vhdl vhdl-verification xilinx xilinx-vivado

Last synced: 15 Apr 2025

https://github.com/sinakarvandi/hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

asic asic-design chisel chisel3 fpga gtkwave modelsim netlist openlane openram verilator verilog vhdl vitis vitis-hls vivado vivado-hls

Last synced: 25 Feb 2026

https://github.com/emanothman21/pdp-11

A simulation to PDP-11 microprocessor with modelsim, The design is a micro-programmed based with an average of 9 clock cycles per instruction.

alu assembler micro-programming microprocessor modelsim pdp-11 pla vhdl

Last synced: 29 May 2026

https://github.com/kazhuu/vhdl-examples

VHDL examples for a different kind of topics

example example-code example-codes example-project examples ghdl hdlcc modelsim vhdl vim vim-hdl

Last synced: 11 Apr 2025

https://github.com/engineermichael/modelsim-altera-project-electronics-

⎔ Using the program ModelSim-Altera, to execute a Synchronous Counter with Asynchronous and Synchronous Reset project by implementing a 2 Bit, 4 Bit, 6 Bit, and 11 Bit for counters by using VHDL code.

altera-de1 altera-fpga altera-quartus modelsim synchronous-counter vhdl-code

Last synced: 26 Feb 2026

https://github.com/mustafahakkoz/mips_projects

A single cycle circuit design with additional instrucitons like JRS, ORI, BGZEAL, SLLV, JMSUB, BALV on ModelSim Simulator is implemented.

assembly computer-organization mips modelsim

Last synced: 23 Mar 2025

https://github.com/mcquerol/electronic-systems

Various electronic systems including ADC/DAC, filters, and simulations using NI Multisim.

adc alu c dac digital-logic filters fpga full-adder half-adder modelsim mux ni-multisim nyquist-frequency op-amp oscilloscope quantized-waves quartus-prime simulation spice systemverilog

Last synced: 19 Jun 2026

https://github.com/zsh811/vhdl-digital-clock-system

A digital clock system implemented with VHDL via Intel Quartus Prime and ModelSim.

digital-clock intel-quartus-prime modelsim vhdl

Last synced: 20 Feb 2026

https://github.com/wyvernsemi/lm32fpga

FPGA development board (DE1) targetted lm32 based systems design for Verilog

altera cpu cyclone fpga latticemico32 modelsim python3 quartus verilog

Last synced: 01 Sep 2025

https://github.com/patsaoglou/built-in-self-test

Built-In-Self-Test blocks using LFSRs and MISRs for a circuit under test made in Verilog

altera bist digital-design lfsr modelsim quartus reliability testbench verilog xilinx

Last synced: 03 Jul 2025

https://github.com/orcalinux/computer-organization-and-architecture

Verilog code examples and materials for Computer Organization.

8086-microprocessor computer-architecture computer-organization modelsim pic programmable-interrupt-controller qu synthesis-project verilog

Last synced: 19 Jan 2026

https://github.com/leobel96/polito-sdi-reflexesanalyzer

Teamwork project of a reflexes analyzer made during the course "Sistemi Digitali Integrati" (Integrated Digital Systems) @ Politecnico di Torino

digital-electronics fpga integrated-circuits modelsim quartus vhdl

Last synced: 05 Jan 2026

https://github.com/dipto9999/scrolling_display_de1-soc

Scrolling Display Implemented With Digital Design Concepts on De1-SoC

de1-soc fpga modelsim quartus-prime systemverilog-hdl

Last synced: 04 Feb 2026

https://github.com/risceirb/risc-v-processor

Processor RISC-V and application

assembly assembly-risc assembly-risc-v branch-predictor enseirb enseirb-matmeca modelsim monocycle-processor pipeline pipeline-processor processor risc-v risc-v-architecture risc-v-architectures risc-v-assembly riscv ufsm

Last synced: 03 Feb 2026

https://github.com/tariqjamel/image-processing-in-verilog

An image processing pipeline written in Verilog that performs RAW Bayer to RGB conversion and applies 3x3 convolution filters like blur and identity for pixel-level image enhancement.

image-processing modelsim pipeline pixel-processing rgb verilog vhdl xilinx xilinx-fpga

Last synced: 07 Feb 2026

https://github.com/leobel96/polito-esd-neuralnetwork

Teamwork project made during the course "Elettronica dei Sistemi Digital" (Electronics of Integrated Systems) @ Politecnico di Torino

digital-filter integrated-circuits modelsim vhdl

Last synced: 09 Feb 2026

https://github.com/siavashshams/arm-processor_with_forwarding_and_sram

The code for the ARM processor with forwarding and SRAM, and the synthesized code for implementation on EP2C70F672C8N FPGA board programmed through Quartus II.

arm forwarding fpga modelsim quartus sram

Last synced: 19 Mar 2026

https://github.com/humbertocg18/pucrs-fsd-2.3-2023.24

Trabalhos, Projetos, Exercícios e aulas realizados em VHDL e Assembly na cadeira de Fundamentos de sistemas digitais, matéria do segundo semestre.

asm assembly-language linux mars mips mips-assembly modelsim pucrs vhd vhdl vhdl-code wave

Last synced: 28 Apr 2026

https://github.com/mohammadmahdi-abdolhosseini/computer-architecture-lab

Computer Architecture Lab - Assignments - Fall 2023

arm-processor fpga modelsim quartus2 systemverilog verilog vhdl

Last synced: 02 Mar 2026

https://github.com/istiak8empire/hands-on-project-of-verilog-hdl

Implementing Hands-on Project of Verilog-HDL

altera arm asic asic-design async fpga intel logic-gates modeling modelsim simulation synthesis systemverilog testbenches verification verilog verilog-hdl vhdl xilinx xilinx-fpga

Last synced: 02 Mar 2026

https://github.com/muntahashams/simulations

this repo contain simulations of various circuits

3phase controlled-rectifier microwind modelsim nanohub power-electronics rectifier simulation ssd thyister uncontrolled-rectifer vlsi vlsi-circuits

Last synced: 31 Jan 2026

https://github.com/jakobod/modelsim-installer

haw install installer modelsim vhdl

Last synced: 03 May 2026

https://github.com/sanugiw/fpga

UA UART communication module using Verilog on a DE0-Nano FPGA with real-time serial data transfer, and verified functionality with a custom test bench.

fpga-programming modelsim systemverilog verilog-hdl

Last synced: 13 Feb 2026

https://github.com/melvinmo/hdl_course_archive

This repository houses my work from the undergraduate hardware description language course in Verilog and the utilization of tools such as ModelSim and Xilinx ISE.

fpga modelsim verilog-hdl xilinx-ise

Last synced: 22 Feb 2026