Projects in Awesome Lists tagged with fpga-programming
A curated list of projects in awesome lists tagged with fpga-programming .
https://github.com/JulianKemmerer/PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
c fpga fpga-acceleration fpga-accelerators fpga-programming hardware hardware-description hardware-description-language high-level-synthesis hls open-source-hardware pipelines python vhdl
Last synced: 22 Apr 2025
https://github.com/juliankemmerer/pipelinec
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
c fpga fpga-acceleration fpga-accelerators fpga-programming hardware hardware-description hardware-description-language high-level-synthesis hls open-source-hardware pipelines python vhdl
Last synced: 15 Apr 2025
https://github.com/calyxir/calyx
Intermediate Language (IL) for Hardware Accelerator Generators
compiler fpga-programming high-level-synthesis intermediate-language open-source-hardware
Last synced: 15 Mar 2025
https://github.com/cornell-zhang/HiSparse
High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
fpga-programming high-level-synthesis open-source-hardware sparse-linear-algebra
Last synced: 21 Apr 2025
https://github.com/pc2/sus-compiler
A new Hardware Design Language that keeps you in the driver's seat
fpga fpga-programming hardware-description-language hdl programming-language tree-sitter
Last synced: 04 Apr 2025
https://github.com/geraked/verilog-rle
Verilog Implementation of Run Length Encoding for RGB Image Compression
compression-algorithm computer-engineering fpga fpga-programming geraked image-compression image-processing ise matlab rabist rle rle-compression-algorithm run-length-encoding student-project verilog verilog-code verilog-hdl xilinx xilinx-fpga yazd-university
Last synced: 19 Apr 2025
https://github.com/jjfumero/tornadovm-examples
Set of examples written for hardware acceleration via TornadoVM
fpga fpga-programming gpu gpuprogramming java jvm opencl parallel-computing ptx spirv tornadovm
Last synced: 17 Nov 2024
https://github.com/anupam-io/es203-coa-cnn
ES-203 Computer Organization & Architecture CNN on FPGA board
cnn cnn-classification cnn-keras cnn-model fpga fpga-programming machine-learning machinelearning verilog vivado
Last synced: 03 Apr 2025
https://github.com/mikeroyal/fpga-guide
FPGA Guide
fpga fpga-board fpga-programming fpga-soc hardware verilog
Last synced: 31 Mar 2025
https://github.com/choaib-elmadi/fpga-programming-for-beginners
A collection of notes, summaries, and projects based on the book "FPGA Programming for Beginners" by Frank Bruno.
electronics embedded embedded-systems fpga fpga-board fpga-programming fpga-soc systemverilog verilog vhdl
Last synced: 16 Mar 2025
https://github.com/jmduarte/hls_hls4ml_tutorial
HLS & hls4ml Tutorial
fpga fpga-firmware fpga-programming high-energy-physics high-level-synthesis hls hls4ml machine-learning particle-physics vitis vivado vivado-hls xilinx xilinx-fpga
Last synced: 06 Jan 2025
https://github.com/clarkfieseln/fpga_hw_sim_fwk_2
FPGA Hardware Simulation Framework
api emulation emulator fpga fpga-programming hdl pygubu pygubu-designer python python-3 python3 simulation simulator vhdl vhdl-code windows windows-10 windows-11 windows10
Last synced: 25 Apr 2025
https://github.com/arasgungore/256-colors-with-vga
A VHDL-based VGA driver to display 256 different colors on a monitor.
256-color 256-colors clock-divider color color-scheme colors colorscheme digital-design fpga fpga-board fpga-programming frequency-divider rgb rgb-color synchronization vga vga-controller vga-driver vhdl vhdl-code
Last synced: 09 Mar 2025
https://github.com/kampi/zybo
Miscellaneous things and projects for my ZYBO and ZYNQ devices.
amd arm c cpp fpga fpga-programming linux vhdl wsl-ubuntu wsl2 xilinx zybo zynq
Last synced: 20 Nov 2024
https://github.com/styczynski/fpga-verilog
Collection of my projects that was made as a part of Warsaw University FPGA course
fpga fpga-board fpga-programming hardware uart verilog vga
Last synced: 05 Mar 2025
https://github.com/choaib-elmadi/getting-started-with-vhdl
Getting started with VHDL: Very High Speed Integrated Circuit Hardware Description Language.
circuit design digital fpga fpga-board fpga-programming fpga-soc hdl vhdl vhdl-code vhdl-examples
Last synced: 16 Mar 2025
https://github.com/ziyue-pan/fpga--jojo
Final project of Digital Logic Design course, a video game.
Last synced: 22 Apr 2025
https://github.com/robseb/rstoolsa10
Source Code of Yocto Layer for accessing FPGA Manager of the Intel (ALTERA) Arria 10 SX SoCFPGA
altera arria10 embedded fpga fpga-programming intel-fpga socfpga visual-studio
Last synced: 14 Apr 2025
https://github.com/benitoss/zxdos
Spartan 6 Lx16 Xilinx FPGA board implementing retro 80's 90's machines
Last synced: 13 Apr 2025
https://github.com/choaib-elmadi/working-with-fpga-and-vhdl
A collection of practical FPGA and VHDL projects using the ALTERA Cyclone V DE-1 SoC board.
electronics embedded-systems fpga fpga-board fpga-programming fpga-soc soc system-on-chip vhdl vhdl-code
Last synced: 22 Mar 2025
https://github.com/robseb/rstoolscy5
Source Code of Yocto Layer for accessing FPGA Manager of the Intel (ALTERA) Cyclone V SoCFPGA
altera cyclone-v embedded fpga fpga-programming intel intel-fpga socfpga visual-studio
Last synced: 14 Apr 2025
https://github.com/choaib-elmadi/risc-v-on-de1-soc-fpga
A simplified RISC-V processor implemented in Verilog and deployed on the DE-1 SoC FPGA board.
de1-soc fpga fpga-board fpga-programming fpga-soc hdl implementation processor programming risc risc-v riscv verilog
Last synced: 14 Apr 2025
https://github.com/choaib-elmadi/working-with-fpga-and-mips
A collection of practical sessions exploring FPGA programming and MIPS-based systems using the ALTERA Cyclone V DE-1 SoC board.
embedded-systems fpga fpga-board fpga-programming fpga-soc mips mips-architecture mips-assembly soc vhdl
Last synced: 22 Mar 2025
https://github.com/engineermichael/-robotic-arm---haddington-dynamics-robotics-engineering-
⎔ Automation in 3D-Printed Robotics
3d-printing ai automation c fpga-programming fpga-soc javascript orcad pcb robotic-arm software software-engineering ui-design
Last synced: 03 Jan 2025
https://github.com/asankasovis/bidirectional_transmitter
📡 This project was intended to develop a bidirectional transmitter and reciever device that uses Visible Light Communication (VLC) technology to transmit and recieve data from one device to another. In its basic form, data is transmitted as pulses of light where on means bit 1 and off means bit 0.
amd cora digilent fpga fpga-programming serial-communication transciever uart-protocol zynq-7000
Last synced: 28 Mar 2025
https://github.com/dineshpinto/timetagger
FPGA programming for nanosecond photon counting
c fpga fpga-programming linux photonics picosecond swig-binding verilog
Last synced: 12 Apr 2025
https://github.com/alicepagano/mapd-a-project-ipbus-filter
FIR filter co-processor implementation in FPGA
Last synced: 16 Mar 2025
https://github.com/akhilrai28/single-port-ram
This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.
digital-circuits fpga fpga-programming hardware hardware-description-language memory-design ram single-port synchronous testbench verilog
Last synced: 02 Apr 2025
https://github.com/asankasovis/eight_bit_computer
🎛️ FPGAs are an interesting invention that is expected to revolutionize the digital industry. This series will focus on building the 8-bit computer that Ben Eater built on his youtube channel. However, it will be done not with actual chips and hardware, but with Verilog code and FPGA simulations.
8bit beneater computer fpga fpga-programming verilog
Last synced: 28 Mar 2025
https://github.com/1c3t3a/canny-zybo-z7
Implementation of a Canny-Edge Detector on a Zybo-Z7 FPGA.
canny-edge-detection fpga-programming verilog-hdl
Last synced: 05 Apr 2025
https://github.com/wissance/quickrs232
A versatile full-duplex RS232 FPGA module with internal FIFO buffer on RX
altera-uart fpga fpga-programming fpga-rs232 rs232 serial-communication serial-communication-fpga uart uart-verilog verilog-library verilog-rs232 verilog-serial-port verilog-uart
Last synced: 04 Apr 2025
https://github.com/lebrancconvas/typescript-for-concept
Clarify anything I'm interested in TypeScript until It can't. (Because TypeScript is good and fit to me for mapping out the domain).
computer-architecture cpu digital-circuit fpga fpga-programming low-byte-productions low-level memory playground-project risc-v riscv typescript virtual-machine vm
Last synced: 26 Apr 2025
https://github.com/skpro-glitch/parallel_multiplier
Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.
asic asic-design fpga fpga-programming multiplier parallel-multiplication register-transfer-level rtl rtl-design systemverilog systemverilog-test-bench verilog-hdl vlsi-design xilinx-vivado
Last synced: 06 Apr 2025
https://github.com/gaikwadabhishek/flappy-bird-fpga-vhdl
Flappy Bird on FPGA using VHDL
altera-fpga cyclone-ii flappy-bird fpga fpga-programming vhdl
Last synced: 03 Apr 2025
https://github.com/emperorpenguin18/assembler
Mini SRC assembler for school project
assembler assembly c c-lang c-language cli fpga fpga-programming risc
Last synced: 31 Mar 2025
https://github.com/rejunity/fpga-icebreaker-racing-the-beam
Playground for graphics experiments running on iCE40 Lattice FPGA with iceBreaker board
fpga fpga-programming hdmi ice40 icebreaker retro vga
Last synced: 24 Mar 2025
https://github.com/peplxx/morse-coder
This project was made for optional fpga project during F23 Computer Architecture course. This is Quartus Project for turning fpga board into morse coder.
fpga-board fpga-programming morse-code quartus-prime verilog
Last synced: 06 Apr 2025
https://github.com/sergz72/fpga
FPGA related stuff
assembler assembly-language bytecode-compiler cpu cyclone forth forth-cpu forth-language fpga fpga-programming gowin java java-cpu risc-v verilog
Last synced: 21 Mar 2025
https://github.com/awrsha/fpga-programming
Advanced FPGA implementations of cutting-edge deep learning models, optimized for high performance and energy efficiency.
cifar-10-dataset cnn fpga fpga-programming genetic-algorithm imagenet real-time resnet-18 systolic-arrays
Last synced: 01 Mar 2025
https://github.com/jn513/estudos_verilog
Exemplos feito em verilog para estudos
fpga fpga-programming hardware verilog verilog-code verilog-hdl
Last synced: 02 Apr 2025
https://github.com/slatyo/sonartracking
Small project to track things with a waterproof sonar sensor
adc arduino dac ds18b20 echo esp esp12f esp8266 fpga fpga-board fpga-programming jsn-sr04t oled-display-ssd1306 sonar tr-89b ultrasonic ultrasonic-distance-sensors vhdl xilinx-fpga xilinx-ise
Last synced: 06 Apr 2025
https://github.com/shuregg/fpga-practicum
learning about FPGA
fpga fpga-programming rtl systemverilog verilog vivado xilinx
Last synced: 31 Mar 2025
https://github.com/gracesevillano/rtic-project-antoine-s-army
This project not only provides hands-on experience with VHDL but also offers insight into the fundamental concepts of CPU architecture and design. It bridges the gap between theoretical knowledge and practical application, using the Nexys4 DDR board as a testbed
fpga-programming nexys4ddr vhdl-code
Last synced: 01 Mar 2025
https://github.com/tahirzia-1/uart-transmitter-and-receiver
A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.
fpga-board fpga-programming fpga-soc nexys4ddr rtl simulation systemverilog testbench uart uart-receiver uart-transmitter uart-verilog verilog verilog-hdl verilog-project vivado vivado-hls vivado-simulator
Last synced: 04 Mar 2025
https://github.com/elecgeek/pulsesgene
Fun project to produce (only) pulses as the MultiSignalGene do, with analogue circuits and FPGA or 74HC logic circuits.
electronics fpga-programming ghdl hardware logic-circuit pcb-design spice vhdl vhdl-code yosys
Last synced: 11 Mar 2025
https://github.com/peplxx/keyboard-driver-vhdl
Driver for handling matrix keyboard 4x4 on FPGA Board
driver fpga fpga-programming hardware keyboard verilog verilog-hdl
Last synced: 06 Apr 2025
https://github.com/charkster/xc3sprog-cmod_a7-rpi
Xc3sprog compiled for Raspberry Pi with support for Numonyx (Micron) N25Q 0x16 memory which is on the Cmod-A7 FPGA board.
cmod-a7 fpga-programming raspberry-pi spi-flash
Last synced: 03 Mar 2025
https://github.com/giljr/logica_programavel
Estudo sobre FPGA - Nesse experimento implementamos a primeira opção de circuitos combinacionais tanto em TTL como em FPGA e os comparamos. Palavras chave: VHDL, FPGA, Cyclone IV, ASIC, Circuitos integrados, TTL, Sinais, ENTITY, ARCHITECTURE, Lógica Booleana, Portas Lógicas, AND, OR, NOT.
altera-fpga altera-quartus fpga fpga-programming vhdl vhdl-examples
Last synced: 10 Mar 2025
https://github.com/kitsunesemcalda/trabalho-pratico-circuitos-digitais
Creating a Implementation about estelar simulator in Verilog
fpga fpga-programming max10-lite star star-simulation
Last synced: 03 Apr 2025
https://github.com/mongshil553/digital-engineering-verilog-assignments
Sophomore 2021 1st Semester Digital Engineering Verilog Assignments
fpga-programming verilog xilinx-vivado
Last synced: 03 Mar 2025
https://github.com/tahirzia-1/risc-v-cpu-core-systemverilog
This repository contains a SystemVerilog implementation of a basic 5-stage pipeline RISC-V processor. The processor includes a register file, ALU, control unit, instruction memory, and data memory. It is designed to run simple assembly programs and includes optimizations for performance such as hazard detection, forwarding, and branch prediction.
alu assembly-language cpu fpga fpga-programming processor registers risc-v riscv riscvprocessor simulation systemverilog verilog vivado
Last synced: 03 Mar 2025
https://github.com/kayejd/nexysa7-fpga-programming
Embedded Programming Projects
embedded-systems fpga-programming verilog vivado
Last synced: 11 Mar 2025
https://github.com/tahirzia-1/digital-clock-verilog
This repository contains a Verilog implementation of a 24-hour digital clock designed for FPGA platforms. The design displays hours, minutes, and seconds on a 7-segment display, providing a complete timekeeping solution that can be easily integrated into various FPGA development boards.
7segment digitalclock fpga fpga-programming fpga-soc nexys4ddr simulation synthesis systemverilog systemverilog-hdl verilog verilog-hdl vivado vivado-simulator
Last synced: 04 Mar 2025
https://github.com/h0nt3d/modulo2345updowncounter
A counter written in VHDL that has been designed to count in radix 8 up and down from 0 to 2344 in radix 14 while displaying the counting on 4 Seven Segment Displays
computer-science counter digital-electronics digital-logic-design electrical-engineering electronics fpga-programming instantiation mod quartus-prime radix seven-segments-display vhdl
Last synced: 25 Feb 2025
https://github.com/skpro-glitch/multi-bit-comparator
Variations of a multi-bit generalized comparator for different area and timing.
altera-quartus comparator digital-design fpga fpga-programming logic-circuit low-power power-gating register-transfer-level rtl rtl-design serial-port serialization verilog-hdl vlsi vlsi-design xilinx-vivado
Last synced: 24 Mar 2025