https://github.com/xilinx/vitis-tutorials

Vitis In-Depth Tutorials

aiengine alveo alveo-u200 alveo-u250 embedded embedded-systems fpga kria kria-som vitis xrt zcu102 zcu104

Last synced: 14 May 2025

https://github.com/Xilinx/XRT

Run Time for AIE and FPGA based platforms

fpga linux-kernel vitis xrt

Last synced: 21 Apr 2025

https://github.com/xilinx/xrt

Run Time for AIE and FPGA based platforms

fpga linux-kernel vitis xrt

Last synced: 10 Feb 2026

https://github.com/xilinx/vitis_accel_examples

Vitis_Accel_Examples

acap alveo fpga-programming soc vitis xilinx zynq

Last synced: 18 Feb 2026

https://github.com/definelicht/hlslib

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

cmake fpga high-level-synthesis hpc intel-fpga intel-fpga-opencl sdaccel vitis vivado-hls xilinx

Last synced: 26 Jan 2026

https://github.com/xilinx/xup_vitis_network_example

VNx: Vitis Network Examples

alveo alveo-card networking vitis vitis-network vnx xilinx

Last synced: 11 Oct 2025

https://github.com/xilinx/vitis_model_composer

Vitis Model Composer Examples and Tutorials

acap aiengine fpga hls vitis

Last synced: 11 Oct 2025

https://github.com/Xilinx/Vitis_Model_Composer

Vitis Model Composer Examples and Tutorials

acap aiengine fpga hls vitis

Last synced: 19 Mar 2025

https://github.com/spcl/apfp

FPGA acceleration of arbitrary precision floating point computations.

arbitrary-precision bignum fpga gmp high-level-synthesis high-performance-computing hls hpc mpfr multiple-precision vitis vivado-hls xilinx

Last synced: 07 Apr 2025

https://github.com/lvgl/lv_port_xilinx_zedboard_vitis

This repository contains a template AMP project for the Zedboard using VGA, FreeRTOS, LVGL and USB peripherals

amd digilent embedded freertos lvgl mouse ntp tcp touchscreen usb vga vitis vivado xilinx zedboard

Last synced: 05 Apr 2025

https://github.com/impetus-udes/rule4ml

Resource Utilization and Latency Estimation for ML on FPGA.

fpga hls keras machine-learning neural-network onnx prediction python pytorch regression-models resource-utilization surrogate-models vitis vivado

Last synced: 21 Jan 2026

https://github.com/jmduarte/hls_hls4ml_tutorial

HLS & hls4ml Tutorial

fpga fpga-firmware fpga-programming high-energy-physics high-level-synthesis hls hls4ml machine-learning particle-physics vitis vivado vivado-hls xilinx xilinx-fpga

Last synced: 11 Sep 2025

https://github.com/sinakarvandi/hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

asic asic-design chisel chisel3 fpga gtkwave modelsim netlist openlane openram verilator verilog vhdl vitis vitis-hls vivado vivado-hls

Last synced: 25 Feb 2026

https://github.com/miranda1000/vivado_ps-pl_data_exchange

Creating a Custom IP for PS-PL data exchange in Vivado

digilent-zybo tutorial vhdl vitis vivado zybo-z7

Last synced: 11 Jan 2026

https://github.com/miranda1000/Vivado_PS-PL_data_exchange

Creating a Custom IP for PS-PL data exchange in Vivado

digilent-zybo tutorial vhdl vitis vivado zybo-z7

Last synced: 16 Mar 2025

https://github.com/autohdw/flames

Flexible Linear Algebra with Matrix-Empowered Synthesis (for Vitis HLS)

cpp fpga high-level-synthesis hls linear-algebra vitis vitis-hls

Last synced: 10 Mar 2026

https://github.com/yasnakateb/vectorops

🏄 Custom IP for vector operations

axi axi-lite custom-ip fpga-accelerator hardware-designs hdl vector vector-operation vector-operations vector-ops vhdl vitis vivado zynq

Last synced: 12 Feb 2026

https://github.com/sinakarvandi/fpga

Random FPGA Projects

chisel3 fpga verilog vhdl vitis vivado zynq

Last synced: 19 Mar 2026

https://github.com/alpyen/zynq-gbcartreader

Embedded Software Development project to read & write GameBoy cartridges.

cpp embedded fpga gameboy gameboy-color vhdl vitis vivado

Last synced: 08 Feb 2026

https://github.com/aryan-programmer/axi_gen_and_sum_primes_fpga

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

artix artix-7 axi axi-lite axi-memory-mapped axi-stream basys3 embedded fpga hls vitis vitis-hls vivado vivado-ip-integrator vivado-vitis xilinx xilinx-fpga xilinx-hls xilinx-vitis xilinx-vivado

Last synced: 19 Mar 2026

https://github.com/lombiq/hastlayer-hardware-framework---vitis

Hardware-side component of Hastlayer for Xilinx Vitis FPGAs. See https://hastlayer.com for details.

fpga vitis xilinx

Last synced: 16 Jan 2026

https://github.com/sped0n/eko

BSc Thesis: Design of Sound Source Localization System Based on FPGA and MEMS Microphone.

fpga gcc-phat i2s-microphone mems-microphone vitis vivado zynq-7020

Last synced: 20 Jan 2026

https://github.com/wakatime/tcl-prompt

Tcl plugin for powerlevel10k style prompt and WakaTime time tracking

expect tcl tk vitis vivado wakatime xsct

Last synced: 19 Mar 2026

https://github.com/babarzkhan/tapasco_counter_versions

acceleration fpga vitis xilinx-fpga

Last synced: 22 Apr 2026

https://github.com/freed-wu/xilinx-language-server

language server and vim plugin for xilinx vivado and vitis

lsp-server vim vim-plugin vitis vivado xdc xilinx xsct xsdb

Last synced: 08 Jan 2026

https://github.com/riyasach189/rfdc_loopback_on_rfsoc4x2

The aim of this project is to demonstrate the working of the RF Data Converter IP by analyzing and replicating a part of the official Xilinx design. The goal is to recreate the radio hierarchy using custom IPs (amplitude controller and packet generator) designed in Vitis HLS 2022.1.

adc dac jupyter-notebook pynq rfdc rfsoc4x2 vitis vitis-hls vivado-hls

Last synced: 27 Feb 2025

https://github.com/steleman/xrt-202420.2.18.179-fc39

Clone of AMD / Xilinx XRT repo from https://github.com/Xilinx/XRT. Major patches and builds / works on Fedora 39.

fedora fpga linux-kernel vitis xilinx xrt

Last synced: 01 May 2026