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An open API service indexing awesome lists of open source software.

Projects in Awesome Lists by Xilinx

A curated list of projects in awesome lists by Xilinx .

https://github.com/xilinx/pynq

Python Productivity for ZYNQ

pynq

Last synced: 11 Oct 2025

https://github.com/Xilinx/PYNQ

Python Productivity for ZYNQ

pynq

Last synced: 07 May 2025

https://github.com/xilinx/vitis-ai

Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.

Last synced: 02 Feb 2026

https://github.com/Xilinx/Vitis-AI

Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.

Last synced: 20 Mar 2025

https://github.com/xilinx/linux-xlnx

The official Linux kernel from Xilinx

Last synced: 10 Apr 2025

https://github.com/Xilinx/linux-xlnx

The official Linux kernel from Xilinx

Last synced: 20 Apr 2025

https://github.com/xilinx/brevitas

Brevitas: neural network quantization in PyTorch

brevitas deep-learning fpga hardware-acceleration neural-networks ptq pytorch qat quantization xilinx

Last synced: 11 Oct 2025

https://github.com/Xilinx/brevitas

Brevitas: neural network quantization in PyTorch

brevitas deep-learning fpga hardware-acceleration neural-networks ptq pytorch qat quantization xilinx

Last synced: 23 Apr 2025

https://github.com/xilinx/embeddedsw

Xilinx Embedded Software (embeddedsw) Development

Last synced: 11 Oct 2025

https://github.com/xilinx/finn

Dataflow compiler for QNN inference on FPGAs

compiler dataflow fpga neural-network quantization

Last synced: 11 Oct 2025

https://github.com/Xilinx/finn

Dataflow compiler for QNN inference on FPGAs

compiler dataflow fpga neural-network quantization

Last synced: 20 Mar 2025

https://github.com/xilinx/dma_ip_drivers

Xilinx QDMA IP Drivers

Last synced: 11 Oct 2025

https://github.com/Xilinx/BNN-PYNQ

Quantized Neural Networks (QNNs) on PYNQ

Last synced: 20 Mar 2025

https://github.com/xilinx/u-boot-xlnx

The official Xilinx u-boot repository

Last synced: 11 Oct 2025

https://github.com/Xilinx/u-boot-xlnx

The official Xilinx u-boot repository

Last synced: 21 Apr 2025

https://github.com/xilinx/xrt

Run Time for AIE and FPGA based platforms

fpga linux-kernel vitis xrt

Last synced: 10 Feb 2026

https://github.com/Xilinx/XRT

Run Time for AIE and FPGA based platforms

fpga linux-kernel vitis xrt

Last synced: 21 Apr 2025

https://github.com/xilinx/hls

Vitis HLS LLVM source code and examples

Last synced: 11 Oct 2025

https://github.com/Xilinx/HLS

Vitis HLS LLVM source code and examples

Last synced: 15 Mar 2025

https://github.com/Xilinx/XilinxTclStore

Xilinx Tcl Store

Last synced: 22 Apr 2025

https://github.com/Xilinx/mlir-aie

An MLIR-based toolchain for AMD AI Engine-enabled devices.

llvm mlir

Last synced: 20 Mar 2025

https://github.com/xilinx/xfopencv

Last synced: 11 Oct 2025

https://github.com/xilinx/chaidnn

HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs

alexnet deep-neural-networks dnn embedded-vision googlenet inference xilinx xilinx-ultrascale-mpsocs

Last synced: 11 Oct 2025

https://github.com/Xilinx/RapidWright

Build Customized FPGA Implementations for Vivado

fpga rapidwright vivado xilinx

Last synced: 21 Apr 2025

https://github.com/xilinx/qemu

Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.

c qemu tcg

Last synced: 11 Oct 2025

https://github.com/xilinx/xilinxvirtualcable

Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable.

Last synced: 11 Oct 2025

https://github.com/xilinx/libsystemctlm-soc

SystemC/TLM-2.0 Co-simulation framework

co-simulation qemu systemc tlm2

Last synced: 11 Oct 2025

https://github.com/Xilinx/qemu

Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.

c qemu tcg

Last synced: 09 Jul 2025

https://github.com/xilinx/finn-examples

Dataflow QNN inference accelerator examples on FPGAs

alveo finn fpga neural-network-accelerators pynq

Last synced: 11 Oct 2025

https://github.com/xilinx/qnn-mo-pynq

Last synced: 11 Oct 2025

https://github.com/Xilinx/XilinxVirtualCable

Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable.

Last synced: 20 Apr 2025

https://github.com/xilinx/device-tree-xlnx

Linux device tree generator for the Xilinx SDK (Vivado > 2014.1)

Last synced: 24 Feb 2026

https://github.com/Xilinx/open-nic

AMD OpenNIC Project Overview

datacenter fpga network-acceleration networking smartnic

Last synced: 13 Apr 2025

https://github.com/xilinx/finn-hlslib

Vitis HLS Library for FINN

Last synced: 11 Oct 2025

https://github.com/Xilinx/libsystemctlm-soc

SystemC/TLM-2.0 Co-simulation framework

co-simulation qemu systemc tlm2

Last synced: 14 Mar 2025

https://github.com/Xilinx/DPU-PYNQ

DPU on PYNQ

pynq

Last synced: 20 Mar 2025

https://github.com/xilinx/graffitist

Graph Transforms to Quantize and Retrain Deep Neural Nets in TensorFlow

deep-neural-networks quantization retraining tensorflow

Last synced: 11 Oct 2025

https://github.com/xilinx/pynq-computervision

Computer Vision Overlays on Pynq

pynq

Last synced: 11 Oct 2025

https://github.com/xilinx/systemctlm-cosim-demo

QEMU libsystemctlm-soc co-simulation demos.

co-simulation qemu systemc tlm2

Last synced: 11 Oct 2025

https://github.com/xilinx/reconic

RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.

Last synced: 18 Feb 2026

https://github.com/Xilinx/systemctlm-cosim-demo

QEMU libsystemctlm-soc co-simulation demos.

co-simulation qemu systemc tlm2

Last synced: 14 Mar 2025

https://github.com/xilinx/mlir-air

Last synced: 25 Dec 2025

https://github.com/xilinx/kria-vitis-platforms

Kria Vitis platforms and overlays

Last synced: 21 Feb 2026

https://github.com/xilinx/vitis_model_composer

Vitis Model Composer Examples and Tutorials

acap aiengine fpga hls vitis

Last synced: 11 Oct 2025

https://github.com/xilinx/pynq-helloworld

This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.

Last synced: 11 Oct 2025

https://github.com/xilinx/open-nic-shell

AMD OpenNIC Shell includes the HDL source files

datacenter fpga network-acceleration smartnic verilog

Last synced: 16 Feb 2026

https://github.com/xilinx/nanotube

Last synced: 11 Oct 2025

https://github.com/Xilinx/nanotube

Last synced: 22 Apr 2025

https://github.com/xilinx/sdaccel-tutorials

SDAccel Development Environment Tutorials

Last synced: 11 Oct 2025

https://github.com/xilinx/accl

Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators

fpga hpc mpi

Last synced: 11 Oct 2025

https://github.com/xilinx/logicnets

Last synced: 11 Oct 2025

https://github.com/Xilinx/kria-vitis-platforms

Kria Vitis platforms and overlays

Last synced: 20 Mar 2025

https://github.com/xilinx/meta-petalinux

meta-petalinux distro layer supporting Xilinx Tools

Last synced: 16 Feb 2026

https://github.com/Xilinx/Vitis_Model_Composer

Vitis Model Composer Examples and Tutorials

acap aiengine fpga hls vitis

Last synced: 19 Mar 2025

https://github.com/Xilinx/logicnets

Last synced: 02 Apr 2025

https://github.com/xilinx/rfsoc-pynq

Python productivity for RFSoC platforms

Last synced: 11 Oct 2025

https://github.com/xilinx/lstm-pynq

Last synced: 11 Oct 2025

https://github.com/xilinx/iiot-eddp

The repository contains the design database and documentation for Electric Drives Demonstration Platform

demo motor-controller

Last synced: 24 Feb 2026

https://github.com/xilinx/ai-model-zoo

Last synced: 15 Feb 2026

https://github.com/xilinx/kria-pynq

PYNQ support and examples for Kria SOMs

Last synced: 11 Oct 2025

https://github.com/xilinx/open-nic-driver

AMD OpenNIC driver includes the Linux kernel driver

datacenter driver linux-kernel smartnic

Last synced: 11 Oct 2025

https://github.com/xilinx/pynq_composable_pipeline

PYNQ Composabe Overlays

composable fpga pynq xilinx

Last synced: 18 Feb 2026

https://github.com/xilinx/chipscopy

ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communication Framework) ChipScope Server (cs_server).

Last synced: 11 Oct 2025

https://github.com/xilinx/xup_high_level_synthesis_design_flow

AMD University Program HLS tutorial

Last synced: 11 Oct 2025

https://github.com/xilinx/gemx

Matrix Operation Library for FPGA https://xilinx.github.io/gemx/

Last synced: 11 Oct 2025

https://github.com/xilinx/qemu-devicetrees

Device trees used by QEMU to describe the hardware

Last synced: 22 Feb 2026

https://github.com/xilinx/xilinxcedstore

This store contains Configurable Example Designs.

Last synced: 17 Feb 2026

https://github.com/xilinx/pynq-networking

Networking Overlay on PYNQ

pynq

Last synced: 15 Feb 2026

https://github.com/xilinx/krs

The Kria Robotics Stack (KRS) is a ROS 2 superset for industry, an integrated set of robot libraries and utilities to accelerate the development, maintenance and commercialization of industrial-grade robotic solutions while using adaptive computing.

acceleration fpga fpga-acceleration gpu-acceleration hardware hardware-acceleration k26 kernels kria kria-som krs kv260 robot-operating-system robotics ros ros2

Last synced: 11 Oct 2025

https://github.com/xilinx/bootgen

bootgen source code

Last synced: 11 Oct 2025

https://github.com/Xilinx/bootgen

bootgen source code

Last synced: 24 Sep 2025

https://github.com/xilinx/alveo-pynq

Introductory examples for using PYNQ with Alveo

alveo aws-f1 pynq xilinx

Last synced: 11 Oct 2025

https://github.com/xilinx/pynq_bootcamp

PYNQ Bootcamp 2019-2024 teaching materials.

Last synced: 11 Oct 2025

https://github.com/xilinx/aved

Alveo Versal Example Design

Last synced: 11 Oct 2025

https://github.com/xilinx/hdmi-modules

Xilinx Soft-IP HDMI Rx/Tx core Linux drivers

Last synced: 11 Oct 2025

https://github.com/xilinx/iiot-spyn

IIoT-SPYN gives users the ability to control, monitor, capture data, visualize and analyze industrial grade motors

fpga pynq pynq-hardware-overlay python sdsoc

Last synced: 11 Oct 2025

https://github.com/xilinx/xup_fpga_vivado_flow

AMD Xilinx University Program Vivado tutorial

fpga hardware vivado xilinx

Last synced: 15 Feb 2026

https://github.com/Xilinx/hdmi-modules

Xilinx Soft-IP HDMI Rx/Tx core Linux drivers

Last synced: 20 Apr 2025