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Projects in Awesome Lists tagged with systemc

A curated list of projects in awesome lists tagged with systemc .

https://github.com/verilator/verilator

Verilator open-source SystemVerilog simulator and lint system

compilers cpp rtl system-verilog systemc verilator verilog verilog-simulator

Last synced: 21 Feb 2026

https://github.com/sergeykhbr/riscv_vhdl

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

cpu debugger qt riscv simulator soc systemc vhdl

Last synced: 22 Apr 2025

https://github.com/accellera-official/systemc

SystemC Reference Implementation

cpp systemc tlm

Last synced: 11 May 2025

https://github.com/mariusmm/RISC-V-TLM

RISC-V SystemC-TLM simulator

risc-v riscv systemc tlm2

Last synced: 21 Nov 2025

https://github.com/tymonx/logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

asic cmake cpp fpga hdl modelsim quartus rtl systemc systemverilog testing-rtl unit-tests uvm verification verilator verilog vivado xilinx

Last synced: 14 Apr 2025

https://github.com/intel/systemc-compiler

This tool translates synthesizable SystemC code to synthesizable SystemVerilog.

clang hardware-designs hls llvm systemc

Last synced: 11 May 2025

https://github.com/xilinx/libsystemctlm-soc

SystemC/TLM-2.0 Co-simulation framework

co-simulation qemu systemc tlm2

Last synced: 11 Oct 2025

https://github.com/nic30/hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

codegen codegenerator compiler fpga hcl hls rtl simulator systemc systemverilog uvm verilog vhdl

Last synced: 08 Apr 2025

https://github.com/Nic30/hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

codegen codegenerator compiler fpga hcl hls rtl simulator systemc systemverilog uvm verilog vhdl

Last synced: 15 Mar 2025

https://github.com/Xilinx/libsystemctlm-soc

SystemC/TLM-2.0 Co-simulation framework

co-simulation qemu systemc tlm2

Last synced: 14 Mar 2025

https://github.com/machineware-gmbh/vcml

A modeling library with virtual components for SystemC and TLM simulators

systemc tlm-models

Last synced: 04 Apr 2026

https://github.com/xilinx/systemctlm-cosim-demo

QEMU libsystemctlm-soc co-simulation demos.

co-simulation qemu systemc tlm2

Last synced: 11 Oct 2025

https://github.com/Xilinx/systemctlm-cosim-demo

QEMU libsystemctlm-soc co-simulation demos.

co-simulation qemu systemc tlm2

Last synced: 14 Mar 2025

https://github.com/Minres/SystemC-Components

A SystemC productivity library: https://minres.github.io/SystemC-Components/

c-plus-plus c-plusplus systemc

Last synced: 11 May 2025

https://github.com/agra-uni-bremen/crave

Constrained random stimuli generation for C++ and SystemC

constrained-random systemc

Last synced: 20 Jan 2026

https://github.com/tymonx/virtio

Virtio implementation in SystemVerilog

cmake fpga hdl model quartus rtl systemc systemverilog verilator verilog virtio vivado xilinx

Last synced: 08 Feb 2026

https://github.com/xilinx/pcie-model

PCI Express controller model

c co-simulation pcie systemc tlm2

Last synced: 11 Oct 2025

https://github.com/nic30/hdlconvertorast

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

codegen codegenerator fpga python systemc systemverilog verilog vhdl

Last synced: 09 Apr 2025

https://github.com/agra-uni-bremen/symex-vp

A concolic testing engine for RISC-V embedded software with support for SystemC peripherals

concolic-execution concolic-testing klee risc-v riscv riscv32 symbolic-execution systemc

Last synced: 20 Jan 2026

https://github.com/machineware-gmbh/viper

An Eclipse 4 RCP based GUI to interact with SystemC simulators

eclipse-rcp systemc

Last synced: 01 Apr 2026

https://github.com/habedi/systemcaccessnoxim

All you need to build and run SystemC and AccessNoxim on your system; SystemC and AccessNoxim are tools to emulate and test network-on-chip (NOC) algorithms

hardware shell simulation systemc

Last synced: 27 Apr 2025

https://github.com/tianzhuqiao/bsmedit

C/C++/SystemC Visualizer

systemc visualizer wxpython

Last synced: 16 May 2025

https://github.com/risto97/pygears-uvm

SystemC UVM environment generator for PyGears components. RTL simulated with Verilator

pygears systemc systemc-uvm-generator uvm verification verilator

Last synced: 10 Oct 2025

https://github.com/riscv-mcu/nuclei_vp

Nuclei Virtual Platform

qbox riscv systemc tlm2 virtual-platform

Last synced: 14 Apr 2025

https://github.com/mvxt/noxim-docker

Repository for Noxim Docker image, which containerizes the Noxim NoC Simulator (see README)

docker docker-image dockerfile noc noxim simulator systemc

Last synced: 20 May 2026

https://github.com/risto97/systemc-ams

SystemC-AMS fork

ams systemc systemc-ams

Last synced: 09 Oct 2025

https://github.com/agra-uni-bremen/hardbound-vp

Virtual Prototype with symbolic execution support and HardBound path analyzer

hardbound memory-safety symbolic-execution systemc virtual-prototyping

Last synced: 20 Jan 2026

https://github.com/mazen-daghari/systemc-first-project

this project is a guide for those want to start using systemc on viusal studio (windows os )

c c-compiler hello-world systemc visual-studio windows

Last synced: 26 Apr 2026

https://github.com/agra-uni-bremen/fdl21-stackuse-vp

Fork of riscv-vp for the FDL21 paper: In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes

hifive1 riot risc-v systemc

Last synced: 20 Jan 2026

https://github.com/tinnyellow/pysystem

🏢 Simplify business management with PYSYSTEM, a Python desktop app for company registration, product handling, and sales order processing.

abstract brasil-api business-management clean-architecture cpf-cnpj-validation cpp cppyy desktop-app docker docker-compose eda edaa excel-import pdf-reports pysystemtrade sales-management systemc systemrdl

Last synced: 29 Apr 2026

https://github.com/risto97/socmake

Build system for RTL and SoC designs

cmake cpu hardware rtl simulation systemc systemonchip systemrdl verilog

Last synced: 23 Aug 2025

https://github.com/eric900115/electronic-system-level-design

The repository contains the coursework in the EE6470 course of NTHU's Electronic System Level Design and Synthesis.

architecture-modeling high-level-synthesis risc-v systemc tlm virtual-platform

Last synced: 13 Mar 2026

https://github.com/northy/parallel-steps-sort-memphis

University assignment, will soon be refactored

memphis network-on-chip systemc

Last synced: 07 Jun 2026

https://github.com/dilawar/tantrika

Tantrika is event-driven neural simulator based on SystemC.

event-driven neural-networks systemc

Last synced: 20 Apr 2025

https://github.com/mdccuva/de-fpga-hh

SystemC code modeling a cycle-accurate Differential Evolution of the Hodgkin-Huxley model

differential-evolution genetic-algorithms hodgkin-huxley-model systemc

Last synced: 15 Mar 2025