Projects in Awesome Lists by ultraembedded
A curated list of projects in awesome lists by ultraembedded .
https://github.com/ultraembedded/riscv
RISC-V CPU Core (RV32IM)
asic cpu fpga pipeline-processor risc-v riscv-linux rv32i rv32im verification verilator verilog
Last synced: 26 Jan 2026
https://github.com/ultraembedded/biriscv
32-bit Superscalar RISC-V CPU
artix-7 asic branch-prediction coremark cpu fpga in-order linux pipelined-processors risc-v riscv-linux rv32i rv32im superscalar verilator verilog xilinx
Last synced: 04 Apr 2025
https://github.com/ultraembedded/cores
Various HDL (Verilog) IP Cores
asic audio fpga i2s rtl sdram spi sram uart usb verilator verilog verilog-components verilog-hdl
Last synced: 25 Jan 2026
https://github.com/ultraembedded/core_ddr3_controller
A DDR3 memory controller in Verilog for various FPGAs
Last synced: 27 Feb 2026
https://github.com/ultraembedded/fpgamp
720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)
artix-7 fpga fpga-media-player hd-video hdmi ir-codes jpeg-decoder mjpeg motion-jpeg risc-v rtos sd-card vga
Last synced: 13 Apr 2025
https://github.com/ultraembedded/core_jpeg
High throughput JPEG decoder in Verilog for FPGA
axi-stream fpga jpeg-decoder mjpeg motion-jpeg verilog verilog-hdl
Last synced: 05 Mar 2026
https://github.com/ultraembedded/openlogicbit
Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.
altera-fpga digital-signal-analyzer fpga ftdi2232h ftdi232h lattice-fpga logic-analyzer verilog xilinx-fpga
Last synced: 08 Mar 2026
https://github.com/ultraembedded/riscv_soc
Basic RISC-V Test SoC
fpga-soc fpga-soc-linux linux risc-v riscv-linux system-on-chip systemc verilog
Last synced: 29 Jul 2025
https://github.com/ultraembedded/exactstep
Instruction set simulator for RISC-V, MIPS and ARM-v6m
armv6 instruction-set-simulator mips mips32 risc-v riscv-simulator riscv32 riscv64
Last synced: 17 Aug 2025
https://github.com/ultraembedded/core_ft60x_axi
FTDI FT600 SuperSpeed USB3.0 to AXI bus master
axi4 bus-master data-acquisition fpga ft600 ftdi-devices usb3 verilog xilinx-fpga
Last synced: 03 May 2025
https://github.com/ultraembedded/libhelix-mp3
Fixed-point MP3 decoder (RISC-V port)
Last synced: 19 Oct 2025
https://github.com/ultraembedded/core_sdram_axi4
SDRAM controller with AXI4 interface
axi4 fpga sdram-controller verilog
Last synced: 03 May 2025
https://github.com/ultraembedded/core_usb_cdc
Basic USB-CDC device core (Verilog)
fpga usb usb-cdc usb-device verilog
Last synced: 14 Feb 2026
https://github.com/ultraembedded/core_dvi_framebuffer
Minimal DVI / HDMI Framebuffer
axi4 dvi fpga framebuffer hdmi verilog video xilinx-fpga
Last synced: 01 Mar 2025
https://github.com/ultraembedded/fat_io_lib
Small footprint, low dependency, C code implementation of a FAT16 & FAT32 driver.
c-library fat16 fat32 filesystem microcontroller
Last synced: 03 May 2025
https://github.com/ultraembedded/core_uriscv
Another tiny RISC-V implementation
Last synced: 14 Feb 2026
https://github.com/ultraembedded/usb2sniffer
USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)
artix-7 fpga lambdaconcept-usb2sniffer-hardware rtl usb usb-analyzer usb-debugging usb-scanning usb-sniffer usb2 verilog wireshark xilinx-vivado
Last synced: 03 Mar 2026
https://github.com/ultraembedded/core_axi_cache
128KB AXI cache (32-bit in, 256-bit out)
Last synced: 21 Feb 2026
https://github.com/ultraembedded/riscv-linux-boot
Trivial RISC-V Linux binary bootloader
atomics bootloader bootstrap linux-kernel opensbi opensbi-qemu-linux risc-v riscv-linux rv32im uart
Last synced: 03 May 2025
https://github.com/ultraembedded/core_usb_uart
USB serial device (CDC-ACM)
fpga serial-port uart usb-cdc usb-device usb-serial verilog
Last synced: 06 Mar 2026
https://github.com/ultraembedded/core_jpeg_decoder
HW JPEG decoder wrapper with AXI-4 DMA
Last synced: 27 Jan 2026
https://github.com/ultraembedded/core_ftdi_bridge
FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
axi4 communications-blocks fpga ftdi ftdi-232h verilog
Last synced: 07 Feb 2026
https://github.com/ultraembedded/riscv32_linux_from_scratch
RISC-V 32-bit Linux From Scratch
linux linux-from-scratch linux-kernel risc-v riscv32
Last synced: 20 Jun 2025
https://github.com/ultraembedded/riscv_sbc
A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
ddr3 linux logic-analyzer risc-v rv32im single-board-computers usb usb2 usb3 usb3300
Last synced: 03 May 2025
https://github.com/ultraembedded/minispartan6-audio
miniSpartan6+ (Spartan6) FPGA based MP3 Player
audio fpga mp3player risc-v rv32im sd-card spartan6 verilog verilog-project
Last synced: 07 Mar 2026
https://github.com/ultraembedded/core_ulpi_wrapper
ULPI Link Wrapper (USB Phy Interface)
fpga ulpi usb usb-interface verilog
Last synced: 03 May 2025
https://github.com/ultraembedded/core_mmc
MMC (and derivative standards) host controller
Last synced: 07 Mar 2026
https://github.com/ultraembedded/core_ram_tester
AXI-4 RAM Tester Component
Last synced: 26 Feb 2026
https://github.com/ultraembedded/librtos
Very basic real time operating system for embedded systems...
Last synced: 09 Oct 2025
https://github.com/ultraembedded/armv6m-sim
Simple instruction set simulator for ARMv6-M (Cortex M0)
armv6-m instruction-set-simulator
Last synced: 03 May 2025
https://github.com/ultraembedded/ecpix-5
Projects for the ECPiX-5 - a ECP5 FPGA board.
Last synced: 30 Jan 2026
https://github.com/ultraembedded/minispartan6
Projects for the Scarab Minispartan6+ FPGA board
Last synced: 06 Mar 2026
https://github.com/ultraembedded/altor32
AltOr32 - Alternative Lightweight OpenRisc CPU
Last synced: 06 Mar 2026
https://github.com/ultraembedded/core_mpx
MPX is a open-source CPU which can execute code compiled for MIPS-I ISA
Last synced: 03 Mar 2026
https://github.com/ultraembedded/xc6_bus_pirate
XC6 Bus Pirate (FPGA based multi-tool)
Last synced: 04 Mar 2026
https://github.com/ultraembedded/ecpix5-test
Test code / bitstreams for the LambdaConcept ECPIX-5 FPGA board
Last synced: 06 Feb 2026
https://github.com/ultraembedded/orangecrab
Test projects for the OrangeCrab ECP5 FPGA board
Last synced: 05 Mar 2026
https://github.com/ultraembedded/riscv-linux-prebuilt
RISC-V Linux prebuilt images
Last synced: 01 Mar 2025
https://github.com/ultraembedded/rp2040_blinky
Simple blinky example for the RP2040 that does not require cmake
Last synced: 21 Jun 2025
https://github.com/ultraembedded/embedded_httpd
Embedded HTTP Server
c esp8266 http-server library webserver
Last synced: 14 May 2026