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Projects in Awesome Lists by ultraembedded
A curated list of projects in awesome lists by ultraembedded .
https://github.com/ultraembedded/riscv
RISC-V CPU Core (RV32IM)
asic cpu fpga pipeline-processor risc-v riscv-linux rv32i rv32im verification verilator verilog
Last synced: 02 Aug 2024
https://github.com/ultraembedded/biriscv
32-bit Superscalar RISC-V CPU
artix-7 asic branch-prediction coremark cpu fpga in-order linux pipelined-processors risc-v riscv-linux rv32i rv32im superscalar verilator verilog xilinx
Last synced: 02 Aug 2024
https://github.com/ultraembedded/cores
Various HDL (Verilog) IP Cores
asic audio fpga i2s rtl sdram spi sram uart usb verilator verilog verilog-components verilog-hdl
Last synced: 02 Aug 2024
https://github.com/ultraembedded/core_ddr3_controller
A DDR3 memory controller in Verilog for various FPGAs
Last synced: 01 Aug 2024
https://github.com/ultraembedded/core_jpeg
High throughput JPEG decoder in Verilog for FPGA
axi-stream fpga jpeg-decoder mjpeg motion-jpeg verilog verilog-hdl
Last synced: 01 Aug 2024
https://github.com/ultraembedded/fat_io_lib
Small footprint, low dependency, C code implementation of a FAT16 & FAT32 driver.
c-library fat16 fat32 filesystem microcontroller
Last synced: 04 Aug 2024
https://github.com/ultraembedded/core_uriscv
Another tiny RISC-V implementation
Last synced: 09 Aug 2024
https://github.com/ultraembedded/core_axi_cache
128KB AXI cache (32-bit in, 256-bit out)
Last synced: 01 Aug 2024