Projects in Awesome Lists tagged with sdram

https://github.com/ultraembedded/cores

Various HDL (Verilog) IP Cores

asic audio fpga i2s rtl sdram spi sram uart usb verilator verilog verilog-components verilog-hdl

Last synced: 25 Jan 2026

https://github.com/nullobject/sdram-fpga

A FPGA core for a simple SDRAM controller.

controller fpga memory sdram

Last synced: 25 Jan 2026

https://github.com/hdl-util/sdram-controller

Generic FPGA SDRAM controller, originally made for AS4C4M16SA

as4c4m16sa controller dram fpga quartus sdram systemverilog

Last synced: 11 Mar 2026

https://github.com/iliasam/stm32f429_vga_examples

Code examples of using STM32F429 for generating VGA image.

dcmi ltdc sdio sdram stm32f429

Last synced: 27 Mar 2026

https://github.com/oscc-ip/sdram

An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.

axi4 fpga sdram tapeout verilog

Last synced: 18 Jan 2026

https://github.com/perehinik/sdram_controller

Verilog SDR SDRAM controller for FPGA Xilinx and Lattice

fpga lattice sdram verilog xilinx

Last synced: 27 Jan 2026

https://github.com/cw1997/sdram-controller

SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol

hardware hardware-designs sdram sdram-controller systemverilog verilog-project