Projects in Awesome Lists tagged with dram

https://github.com/liquidctl/liquidctl

Cross-platform CLI and Python drivers for AIO liquid coolers and other devices

aquacomputer asus corsair cross-platform dram driver evga fan-controller gigabyte graphics-card led-controller liquid-cooler nzxt power-supply python

Last synced: 11 Dec 2025

https://github.com/platformlab/ramcloud

**No Longer Maintained** Official RAMCloud repo

dram fault-tolerance key-value low-latency storage

Last synced: 05 Apr 2025

https://github.com/PlatformLab/RAMCloud

**No Longer Maintained** Official RAMCloud repo

dram fault-tolerance key-value low-latency storage

Last synced: 10 May 2025

https://github.com/CMU-SAFARI/ramulator2

Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf

dram memory simulation

Last synced: 11 May 2025

https://github.com/umd-memsys/DRAMSim2

DRAMSim2: A cycle accurate DRAM simulator

c-plus-plus computer-architecture dram simulator

Last synced: 21 Apr 2025

https://github.com/hdl-util/sdram-controller

Generic FPGA SDRAM controller, originally made for AS4C4M16SA

as4c4m16sa controller dram fpga quartus sdram systemverilog

Last synced: 11 Mar 2026

https://github.com/blark/a500plus-chipram-expansion

A 1MB chip RAM expansion for the A500+

a500 amiga amiga-hardware dram retrocomputing

Last synced: 11 Feb 2026

https://github.com/saiteja-talluri/microarchitectural-attacks

Implementation of flush + reload attack to extract private key from the GnuPG implementation of RSA.

cache dram flush-reload rsa

Last synced: 12 May 2025

https://github.com/adarshpatil/dve

Improving DRAM Reliability and Performance On-Demand via Coherent Replication [ISCA 2021]

coherence dram reliability replication sockets

Last synced: 24 Jan 2026

https://github.com/cmu-safari/harp

HARP is a memory error profiling algorithm (i.e., for identifying error-prone cells) designed for use with memory chips that use on-die error-correcting codes (ECC). This tool uses Monte-Carlo simulation to evaluate HARP and other error profilers. HARP and this tool are described in the 2021 MICRO paper by Patel et al.: https://arxiv.org/abs/2109.12697.

dram error-correcting-codes error-correction monte-carlo reliability simulator