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Projects in Awesome Lists tagged with quartus

A curated list of projects in awesome lists tagged with quartus .

https://github.com/hdl-util/hdmi

Send video/audio over HDMI on an FPGA

altera audio dvi fpga hdlmake hdmi intel quartus systemverilog video vivado xilinx

Last synced: 25 Jan 2026

https://github.com/tymonx/logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

asic cmake cpp fpga hdl modelsim quartus rtl systemc systemverilog testing-rtl unit-tests uvm verification verilator verilog vivado xilinx

Last synced: 14 Apr 2025

https://github.com/PyFPGA/pyfpga

A Python package to use FPGA development tools programmatically.

diamond fpga ghdl icestorm ise libero nextpnr python quartus tcl trellis vivado yosys

Last synced: 18 Mar 2025

https://github.com/hdl-util/sdram-controller

Generic FPGA SDRAM controller, originally made for AS4C4M16SA

as4c4m16sa controller dram fpga quartus sdram systemverilog

Last synced: 11 Mar 2026

https://github.com/halfmanhalftaco/fpga-docker

Tools for running FPGA vendor toolchains with Docker

altera fpga lattice quartus verilog vhdl xilinx

Last synced: 06 Apr 2025

https://github.com/tymonx/virtio

Virtio implementation in SystemVerilog

cmake fpga hdl model quartus rtl systemc systemverilog verilator verilog virtio vivado xilinx

Last synced: 08 Feb 2026

https://github.com/mbtaylor1982/resdmac

Verilog code to replace the Commodore SDMAC found in the A3000

altera-fpga amiga amiga-hardware intel-fpga kicad open-source quartus verilog

Last synced: 03 Feb 2026

https://github.com/hell03end/verilog-uart

Simple 8-bit UART realization on Verilog HDL.

fpga hdl quartus uart verilog

Last synced: 17 Jan 2026

https://github.com/Elphel/vdt-plugin

mirror of https://git.elphel.com/Elphel/vdt-plugin

cocotb eclipse eclipse-plugin gtkwave icarus-verilog ide quartus verilog vivado

Last synced: 22 Jul 2025

https://github.com/theypsilon/quartus-lite-c5-dockerized

Quartus Lite (Cyclone V environment) Dockerized

docker fpga linux mister quartus

Last synced: 01 Aug 2025

https://github.com/jonpalmisc/usb_blaster_arm64

Altera USB Blaster drivers for Windows 11 Arm

altera fpga quartus

Last synced: 08 Oct 2025

https://github.com/phrb/legup-tuner

Autotuning High-Level Synthesis for FPGAs, published @ ReConFig '17

autotuning fpgas high-level-synthesis legup opentuner quartus

Last synced: 09 Aug 2025

https://github.com/robseb/niosii_eclipsecompproject

Automatically create a NIOS II Eclipse Project with the latest FreeRTOS Version, the Intel hwlib and more...

arria-v arria10 c custom-eclipse cyclone-v eclipse freertos intel intel-fpga intel-quartus-prime max10 nios-ii python-script quartus soc-fpga

Last synced: 14 Apr 2025

https://github.com/peter-tanner/intel-quartus-dark-mode-windows

A script to convert the Intel Quartus IDE to dark mode using QDarkStyleSheet with some modifications.

dark-mode dark-theme fpga ide intel quartus quartus-prime theme

Last synced: 09 Apr 2025

https://github.com/charlie5dh/risc-v-single-cycle-up

Design and implementation in VHDL for FPGAs of a single cycle RISC-V based architecture

fpga microprocessors quartus risc-v vhdl vhdl-code

Last synced: 03 Mar 2026

https://github.com/vitalych/fpga-gameoflife

A game-of-life implementation for the FPGA4U board, with SDRAM, RS232 UART, and VGA controllers

bitmap dithering fpga fpga4u game-of-life image quartus rs232 sdram uart vga

Last synced: 18 Mar 2026

https://github.com/patsaoglou/jtag-ieee-1149.1

Basic JTAG standard implementation in Verilog and integration with a CUT

digital-design jtag jtag-boundary-scan jtag-probe modelsi quartus reliability tcl testbench verilo

Last synced: 30 Jan 2026

https://github.com/alyssonmach/logic-circuits

Simulations made in the UFCG logic circuit laboratory.

laboratory logic-circuit logisim quartus ufcg verilog

Last synced: 19 Mar 2026

https://github.com/patsaoglou/built-in-self-test

Built-In-Self-Test blocks using LFSRs and MISRs for a circuit under test made in Verilog

altera bist digital-design lfsr modelsim quartus reliability testbench verilog xilinx

Last synced: 03 Jul 2025

https://github.com/marekpikula/quartus-sv-gotchas

Document describing different gotchas in Intel Quartus SystemVerilog code synthesis.

quartus rtl systemverilog

Last synced: 19 Mar 2026

https://github.com/wyvernsemi/lm32fpga

FPGA development board (DE1) targetted lm32 based systems design for Verilog

altera cpu cyclone fpga latticemico32 modelsim python3 quartus verilog

Last synced: 01 Sep 2025

https://github.com/saturn77/monitorx

An example of using Nios to monitor FPGA operations in VHDL.

nios quartus vhdl

Last synced: 09 Mar 2026

https://github.com/iamgroooooot/autobar-digital-design

논리회로 팀 프로젝트

circuit-design quartus vbnet

Last synced: 05 Mar 2026

https://github.com/helcsnewsxd/famaf-computer_science-computer_architecture

Laboratorios, prácticos y teóricos de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)

armv8 computer-architecture famaf-unc hardware-description-language labs optimization pipelined-processors processor-architecture quartus system-verilog theory university-subjects

Last synced: 28 Feb 2025

https://github.com/weizujie/quartus-example

《EDA实验》网课的作业

eda quartus

Last synced: 03 Jan 2026

https://github.com/leobel96/polito-sdi-reflexesanalyzer

Teamwork project of a reflexes analyzer made during the course "Sistemi Digitali Integrati" (Integrated Digital Systems) @ Politecnico di Torino

digital-electronics fpga integrated-circuits modelsim quartus vhdl

Last synced: 05 Jan 2026

https://github.com/siavashshams/arm-processor_with_forwarding_and_sram

The code for the ARM processor with forwarding and SRAM, and the synthesized code for implementation on EP2C70F672C8N FPGA board programmed through Quartus II.

arm forwarding fpga modelsim quartus sram

Last synced: 19 Mar 2026

https://github.com/itreza7/river-raid-atari-game-vhdl

Atari River Raid game programming project using VHDL programming language and FPGA Quartus board

fpga fpga-game fpga-quartus-board quartus vhdl vhdl-examples vhdl-game vhdl-programming-language

Last synced: 29 Jan 2026

https://github.com/bakxy/vhdl-qqs

This project aims to automate the creation of test benches and support files for FPGA designs created using Quartus from Intel. By integrating a custom extension into VS Code, users can efficiently set up simulation environments with minimal manual effort.

fpga intel-fpga open-source quartus questasim simulation testbench-generation typescript vhdl visual-studio-code vscode vscode-extension

Last synced: 10 May 2026

https://github.com/yappy2000d/fpga-make-win

Use the make tool to automate your work in CLI.

makefile quartus verilog

Last synced: 20 Mar 2025

https://github.com/shpegun60/cnt_dly_slg46620

microcircuit SLG46620 CNT/DLY2/FSM0 (from dialog semiconductor company) SystemVerilog interpretation. Dataseet is: https://www.dialog-semiconductor.com/sites/default/files/slg46620r115_10282019.pdf Simulation: QuestaSim x64 ver2020.1 Needed simulation libraries: altera_primitives (build: $projectSource/verification/altera_primitives)

dialog-semiconductor quartus slg46620 systemverilog

Last synced: 16 Mar 2026

https://github.com/russellwzr/design-and-implementation-of-a-simple-cpu

Design-and-implementation-of-a-simple-CPU

cpu-design fpga quartus

Last synced: 19 Feb 2026

https://github.com/rdsik/schoolriscv

CPU microarchitecture, step by step

assembly makefile modelsim quartus verilog-hdl

Last synced: 04 Oct 2025

https://github.com/wassimhedfi/nios-ii-ip-core

This project involves configuring a NIOS II softcore processor on the Altera DE10-Lite FPGA using Quartus Prime. It includes the creation of a custom Board Support Package (BSP), hardware abstraction layer (HAL), and drivers to optimize processor performance.

altera-fpga eclipse-ide embedded-c hal nios-ii quartus

Last synced: 21 Feb 2026

https://github.com/aashrafh/cmp201a

Labs, Assembly Codes ,and Assignments for CMP 201 A (Microprocessor Systems) course

assembly assembly-8086 assembly-x86 microprocessors microprocessors-course quartus quartus-prime

Last synced: 31 Mar 2025

https://github.com/no2chem/quartusld-docker

🐳🔒Run the Intel Quartus License Server in Docker

docker flexlm fpga intel quartus

Last synced: 11 Jun 2025

https://github.com/hbina/mips_processor

MIPS processor written in VHDL

mips quartus vhdl

Last synced: 22 Feb 2026

https://github.com/takeshiyoshikawa/buttons_control_led

This project maps the behavior between input buttons and output LEDs using Quartus II 13.0sp platform alongside with Qsys. Moreover, a C source file to control the components created beforehand.

c embedded-systems quartus

Last synced: 25 Mar 2025

https://github.com/davidf1000/sistemdigital_vhdl

Final Project for Digital System Lab. Flappy Bird Imitation Game created using VHDL for FPGA DE1.

fpga quartus verilog vhdl

Last synced: 29 Jan 2026

https://github.com/farhantips/vlsi-design

This repository covers VLSI Design concepts using Microwind, Quartus, and Waveforms, focusing on digital circuit design, FPGA implementation, and HDL for integrated circuit development.

cmos-circuits layouts microwind mux quartus vending-machine very-large-scale-integration vlsi vlsi-design waveforms

Last synced: 17 Feb 2026

https://github.com/azrielx86/laboratoriooac2025-2

Prácticas de laboratorio para el laboratorio de Organización y Arquitectura de Computadoras - Semestre 2025-2

quartus questasim vhdl

Last synced: 29 Jan 2026

https://github.com/moeeinaali/ce323-ca

Solutions to Dr. Arshadi's CE323: Computer Architecture Course (Sharif University of Technology - Spring 2024)

architecture circuit logic proteus quartus quartus2

Last synced: 02 Feb 2026