Ecosyste.ms: Awesome
An open API service indexing awesome lists of open source software.
Projects in Awesome Lists by hdl-util
A curated list of projects in awesome lists by hdl-util .
https://github.com/hdl-util/sdram-controller
Generic FPGA SDRAM controller, originally made for AS4C4M16SA
as4c4m16sa controller dram fpga quartus sdram systemverilog
Last synced: 15 Nov 2024
https://github.com/hdl-util/mipi-demo
MIPI CSI-2 + MIPI CCS Demo
mipi mipi-camera mipi-ccs mipi-csi-receiver
Last synced: 15 Nov 2024
https://github.com/hdl-util/mipi-csi-2
Capture images/video from a Raspberry Pi Camera (MIPI CSI-2) with an FPGA
Last synced: 15 Nov 2024
https://github.com/hdl-util/hdmi-demo
Demo of hdmi on at 720p with VGA-compatible text mode and sound
Last synced: 15 Nov 2024
https://github.com/hdl-util/i2c
Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
Last synced: 15 Nov 2024
https://github.com/hdl-util/vga-text-mode
VGA-compatible text mode functionality
Last synced: 15 Nov 2024
https://github.com/hdl-util/image-processing
SystemVerilog code for image processing tasks like demosaicing
Last synced: 15 Nov 2024
https://github.com/hdl-util/sound
Various sound waves and audio mixing capabilities
Last synced: 15 Nov 2024
https://github.com/hdl-util/clock-domain-crossing
Utilities for clock-domain crossing with an FPGA
clock-domain-crossing clock-domains clock-synchronization fpga systemverilog verilog
Last synced: 15 Nov 2024
https://github.com/hdl-util/rand
Random number generators such as LFSRs, LHCAs
Last synced: 15 Nov 2024
https://github.com/hdl-util/gray-code
Generate a gray code of arbitrary width in SystemVerilog
code coding fpga gray gray-code graycode systemverilog
Last synced: 15 Nov 2024