Projects in Awesome Lists tagged with altera
A curated list of projects in awesome lists tagged with altera .
https://github.com/pconst/basic_verilog
Must-have verilog systemverilog modules
altera debounce delay encoder fifo fpga hls pwm spi-interface spi-master synchronizer tcl uart uart-controller uart-protocol uart-receiver uart-tx uart-verilog verilog xilinx
Last synced: 27 Jan 2026
https://github.com/pConst/basic_verilog
Must-have verilog systemverilog modules
altera debounce delay encoder fifo fpga hls pwm spi-interface spi-master synchronizer tcl uart uart-controller uart-protocol uart-receiver uart-tx uart-verilog verilog xilinx
Last synced: 14 Mar 2025
https://github.com/olofk/edalize
An abstraction library for interfacing EDA tools
altera eda fossi fpga ghdl icarus-verilog icestorm lattice modelsim riviera-pro simulation spyglass synthesis systemverilog verilator verilog vhdl vivado xilinx yosys
Last synced: 14 May 2025
https://github.com/VLSI-EDA/PoC
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
altera asic fpga hardware-designs hardware-libraries hardware-modules lattice osvvm poc-library python regression-testing simulation synthesis testbenches uvvm verification vhdl vlsi vunit xilinx
Last synced: 22 Apr 2025
https://github.com/hukenovs/intfftk
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
altera cooley-tukey-fft digital-signal-processing dsp fast-convolutions fast-fourier-transform fft fpga integer-arithmetic radix-2 route-optimization verilog vhdl vivado xilinx
Last synced: 14 Feb 2026
https://github.com/BrianHGinc/BrianHG-DDR3-Controller
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
altera ddr3 fpga hdl intel lattice systemverilog testbenches verilog xilinx
Last synced: 15 Jun 2025
https://github.com/hukenovs/fp23fftk
Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
altera chirp convolution convolution-filter cooley-tukey-fft digital-signal-processing dsp fast-convolutions fast-fourier-transform fft floating-point fpga frequency-analysis ieee754 matlab octave radix-2 verilog vhdl xilinx
Last synced: 15 May 2025
https://github.com/robseb/hps2fpgamapping
SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
altera altera-fpga bootloader can-bus embedded-linux fpga fpga-configuration fpga-fabric fpga-soc hps intel intel-fpga linux mapping-hps-peripherals python-script quartus-prime rsyocto soc-fpga
Last synced: 14 Apr 2025
https://github.com/delhatch/spectrum
Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions. Nios just reads the FFT result and draws the display bars. VGA frame buffer on-chip. VGA signals generated on-chip. See the included video files to watch it in action.
altera audio-analysis de2-115 fft fpga rtaudio spectrum-analyzer verilog vga vga-frame-buffer
Last synced: 03 Mar 2026
https://github.com/dilshan/max2-audio-dac
24-bit Stereo Audio DAC for Raspberry Pi
altera audio cpld dac epm240t100c5n i2s-audio r-2r raspberry-pi
Last synced: 16 Jan 2026
https://github.com/thotypous/alterajtaguart
Altera JTAG UART wrapper for Bluespec
altera bluespec hardware-libraries jtag uart usb-serial-adapters
Last synced: 02 Apr 2026
https://github.com/robseb/meta-intelfpga
Yocto Project BSP meta-layer for Intel (ALTERA) SoC-FPGAs (SoCFPGA) - with step by step guide
altera arria-v arria10 bsp-layer cyclone-v development-tools fpga-configuration fpga-fabric intel-fpga intel-soc-fpgas linux-distribution rsyocto soc-fpga soc-fpga-linux yocto-layer yocto-meta
Last synced: 30 Oct 2025
https://github.com/wissance/quickspi
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
altera axi axi-interfaces bit-oriented-spi dragster-spi fpga hard-spi soft-spi spi spi-fpga spi-hdl spi-interface spi-ip-core spi-pld verilog-components verilog-hdl verilog-snippets verilog-spi xilinx-fpga xilinx-vivado
Last synced: 16 Jan 2026
https://github.com/tomverbeure/intel_jtag_uart
A Python module to interact with an Intel JTAG UART
altera fpga intel jtag jtag-atlantic python uart
Last synced: 08 May 2025
https://github.com/anthony-bernaert/ftdi-jtag-programmer
FTDI-based JTAG Programmer Circuit for FPGAs
altera fpga ftdi intel-fpga jtag lattice pcb-design programmer serial-port uart usb xilinx
Last synced: 08 Apr 2026
https://github.com/delhatch/red_tracker
Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. See the video. Pure Verilog. (No soft-core processor.)
altera de2-115 fpga image-processing verilog vga vga-controller
Last synced: 06 Mar 2026
https://github.com/robseb/django2fpgademo
Demonstration how to build a Management Web interface to interact with the FPGA fabric and change the FPGA configuration with the Django Framework
adc altera cyclone-v de10-nano de10-standard de10nano django django-framework fpga-configuration fpga-data fpga-fabric intel-fpga rsyocto sensor-data soc-fpga
Last synced: 14 Apr 2025
https://github.com/hukenovs/adc_configurator
ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
adc adc-configurator altera analog-signals cic dac ddc ddr dds digital-signal-processing dsp fir jesd204b serdes-mode serial-interface vhdl xilinx
Last synced: 02 Jan 2026
https://github.com/lombiq/hastlayer-hardware-framework---catapult
Hardware-side component of Hastlayer for Microsoft Project Catapult FPGAs. See https://hastlayer.com for details.
altera fpga intel microsoft-catapult
Last synced: 30 Jan 2026
https://github.com/hukenovs/fp32_logic
Floating point FP32 core HDL. For Xilinx FPGAs. Include base converters and some math functions.
altera digital-signal-processing dsp floating-point fpga ieee-754 ieee754 integer-arithmetic verilog vhdl xilinx
Last synced: 17 Mar 2026
https://github.com/ahmedsobhy01/aes-verilog
An implementation of the Advanced Encryption Standard (AES) encryption algorithm using Verilog supporting AES-128, AES-192, and AES-256 encryption/decryption
aes aes-128 aes-192 aes-256 altera decryption encryption fpga verilog
Last synced: 23 Jan 2026
https://github.com/jonpalmisc/usb_blaster_arm64
Altera USB Blaster drivers for Windows 11 Arm
Last synced: 08 Oct 2025
https://github.com/paebbels/pyipcmi
A Python-based IP Core Management Infrastructure.
altera database infrastructure intel ip-core modelsim python3 quartus-prime questasim riviera-pro simulation synthesis vhdl vhdl-verification xilinx xilinx-vivado
Last synced: 15 Apr 2025
https://github.com/itzzinfinity/100-days-of-rtl
Trying to get a new skill
altera digital electronics gowin modelsim quartus-prime rtl testbench verilog vivado xilinx xilinx-vivado
Last synced: 24 Jan 2026
https://github.com/addisonelliott/logifindfpgatest
This is a Quartus Prime FPGA project testing the functionality of the LogiFind Altera Cyclone IV EP4CE6E22C8N Development Board. This product can also be found on eBay where I bought it from. I hope to provide base code that will help others in their learning with this development board.
7-segment altera buzzer cyclone-iv easyfpga ep4ce6e22c8n fpga ir-receiver logifind nec-verilog pl2303 quartus-prime uart-verilog verilog verilog-hdl
Last synced: 07 Jan 2026
https://github.com/izyasoft/easyhdllib
A coocbook of HDL (primarily Verilog) modules
altera clock-divider fifo fpga frequencies frequency-analysis hdl verilog verilog-components verilog-hdl verilog-library verilog-snippets xilinx-fpga
Last synced: 19 Jan 2026
https://github.com/dmf444/cscb58-final_project
A (sucessful) attempt at a making guitar hero for a DE2-115 board
altera cscb58 guitar-hero verilog vga
Last synced: 13 Feb 2026
https://github.com/delhatch/pure_mandel
FPGA paramatized mandelbrot generator. I have tested instantiating 4, 8, and 12 calculating engines. It has a built-in VGA controller (at 640x480) with internal dual-port RAM as the frame buffer. With 4 engines it runs at 100 MHz (5 frames/sec). With 12 engines, at 112 MHz, it hits 20.5 frames/sec.
altera de2-115 fpga mandel mandelbrot verilog vga vga-controller
Last synced: 06 Mar 2026
https://github.com/robseb/rstoolsa10
Source Code of Yocto Layer for accessing FPGA Manager of the Intel (ALTERA) Arria 10 SX SoCFPGA
altera arria10 embedded fpga fpga-programming intel-fpga socfpga visual-studio
Last synced: 05 Oct 2025
https://github.com/mshr-h/fibonacci_verilog
fibonacci number calculator written in Verilog-HDL
altera fibonacci fibonacci-numbers iverilog verilog-hdl
Last synced: 18 Mar 2026
https://github.com/robseb/rstoolscy5
Source Code of Yocto Layer for accessing FPGA Manager of the Intel (ALTERA) Cyclone V SoCFPGA
altera cyclone-v embedded fpga fpga-programming intel intel-fpga socfpga visual-studio
Last synced: 23 Aug 2025
https://github.com/suda-morris/fpga-demos
Getting started with Altera FPGA using Quartus Prime Lite17.1
Last synced: 25 Jan 2026
https://github.com/wyvernsemi/lm32fpga
FPGA development board (DE1) targetted lm32 based systems design for Verilog
altera cpu cyclone fpga latticemico32 modelsim python3 quartus verilog
Last synced: 01 Sep 2025
https://github.com/montao/nios2-mmu
Design MMU for socfpga-linux 4.11. Test with Altera DE2-115.
altera hardware-designs mmu nios2 quartus-prime
Last synced: 19 Jan 2026
https://github.com/patsaoglou/built-in-self-test
Built-In-Self-Test blocks using LFSRs and MISRs for a circuit under test made in Verilog
altera bist digital-design lfsr modelsim quartus reliability testbench verilog xilinx
Last synced: 03 Jul 2025
https://github.com/rauhul/ece385
Digital Systems Laboratory UIUC FA 2016
altera fpga quartus-prime systemverilog verilog
Last synced: 18 Mar 2026
https://github.com/alexanderepstein/snake
Simple snake game written in C for the Altera DE0-CV FPGA
Last synced: 31 Dec 2025
https://github.com/istiak8empire/hands-on-project-of-verilog-hdl
Implementing Hands-on Project of Verilog-HDL
altera arm asic asic-design async fpga intel logic-gates modeling modelsim simulation synthesis systemverilog testbenches verification verilog verilog-hdl vhdl xilinx xilinx-fpga
Last synced: 02 Mar 2026
https://github.com/mcleber/bug_fixes_and_configuration_files
This repository compiles notes, fixes, and configuration files that address common issues and bugs encountered during the installation and use of various software tools on both Linux and Windows platforms.
altera altera-fpga altera-quartus de1-soc gowin gowin-eda monitor-program quartus-prime questasim tang tang-primer xilinx xilinx-fpga xilinx-vivado zynq
Last synced: 26 Jan 2026
https://github.com/rezapace/golang-altera
berisikan tugas dan materi pada kampusmerdeka (100% - Mastering Golang Programming) "Repo Go-muhammad-reza-hidayat (rezapace) - proyek Go dengan dokumentasi baik, dukungan Docker."
altera altera-academy git-reza go golang golang-examples webkumal-projek
Last synced: 11 Mar 2025
https://github.com/tiacsys/ghrd-socfpga
Golden Hardware Reference Designs (GHRD) for System On Chips in FPGA (SOCFPGA)
altera ghrd intel max10 quartus-prime socfpga
Last synced: 03 Jan 2026
https://github.com/rezapace/miniprojek
miniprojek altera golang "Repo "miniprojek" oleh rezapace: Backend Go untuk manajemen kafe. Struktur terorganisir, dukungan Docker, dokumentasi lengkap, dan skema database SQL."
altera altera-academy backend git-reza go kampus-merdeka kumal-projek miniprojek webkumal
Last synced: 21 May 2026
https://github.com/montao/opencpu
:octocat: The open 4-bit system for Altera DE2 drawn and compiled with Quartus
altera cpu hardware quartus-prime
Last synced: 06 Apr 2025