Projects in Awesome Lists tagged with uart-receiver
A curated list of projects in awesome lists tagged with uart-receiver .
https://github.com/pconst/basic_verilog
Must-have verilog systemverilog modules
altera debounce delay encoder fifo fpga hls pwm spi-interface spi-master synchronizer tcl uart uart-controller uart-protocol uart-receiver uart-tx uart-verilog verilog xilinx
Last synced: 27 Jan 2026
https://github.com/pConst/basic_verilog
Must-have verilog systemverilog modules
altera debounce delay encoder fifo fpga hls pwm spi-interface spi-master synchronizer tcl uart uart-controller uart-protocol uart-receiver uart-tx uart-verilog verilog xilinx
Last synced: 14 Mar 2025
https://github.com/tahirzia-1/uart-transmitter-and-receiver
A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.
fpga-board fpga-programming fpga-soc nexys4ddr rtl simulation systemverilog testbench uart uart-receiver uart-transmitter uart-verilog verilog verilog-hdl verilog-project vivado vivado-hls vivado-simulator
Last synced: 04 Mar 2025
https://github.com/maxboro/emulated-uart-connection
Device connection and data transmission via UART - simple example
c-language python uart-communication uart-receiver uart-transmitter
Last synced: 19 May 2026
