Projects in Awesome Lists tagged with vivado-hls
A curated list of projects in awesome lists tagged with vivado-hls .
https://github.com/fastmachinelearning/hls4ml
Machine learning on FPGAs using HLS
fpga hls intel-hls keras machine-learning neural-network onnx python pytorch vivado vivado-hls
Last synced: 09 Apr 2025
https://github.com/spcl/dace
DaCe - Data Centric Parallel Programming
cuda fpga high-level-synthesis high-performance-computing programming-language vivado-hls
Last synced: 11 Apr 2025
https://github.com/spcl/gemm_hls
Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
fpga high-level-synthesis hls vivado-hls
Last synced: 12 Apr 2025
https://github.com/spcl/hls_tutorial_examples
Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
fpga high-level-synthesis hls intel-fpga opencl vivado-hls
Last synced: 19 Dec 2024
https://github.com/UCLA-VAST/AutoBridge
[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
floorplan fpga frequency hls-compilation hls-designs vivado-hls xilinx
Last synced: 21 Apr 2025
https://github.com/yangjl-cs/stereo-vision-fpga
Real-time binocular stereo vision FPGA system with OV5640 cameras
Last synced: 15 Mar 2025
https://github.com/spcl/apfp
FPGA acceleration of arbitrary precision floating point computations.
arbitrary-precision bignum fpga gmp high-level-synthesis high-performance-computing hls hpc mpfr multiple-precision vitis vivado-hls xilinx
Last synced: 07 Apr 2025
https://github.com/zhutmost/stereo-vision-fpga
Real-time binocular stereo vision FPGA system with OV5640 cameras
Last synced: 23 Feb 2025
https://github.com/jmduarte/hls_hls4ml_tutorial
HLS & hls4ml Tutorial
fpga fpga-firmware fpga-programming high-energy-physics high-level-synthesis hls hls4ml machine-learning particle-physics vitis vivado vivado-hls xilinx xilinx-fpga
Last synced: 06 Jan 2025
https://github.com/spcl/nbody_hls
Implementation of the N^2-formulation of N-body simulation with Vivado HLS for SDAccel platforms.
fpga high-level-synthesis hls vivado-hls
Last synced: 07 Apr 2025
https://github.com/sinakarvandi/hardware-design-stack
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
asic asic-design chisel chisel3 fpga gtkwave modelsim netlist openlane openram verilator verilog vhdl vitis vitis-hls vivado vivado-hls
Last synced: 11 Mar 2025
https://github.com/spcl/stencil_hls
Implementation of time and space-tiled stencil in Vivado HLS.
fpga high-level-synthesis hls vivado-hls
Last synced: 07 Apr 2025
https://github.com/duartegalvao/arduzynq-tutorials
Simple tutorials for getting started with programming on Trenz ArduZynq boards.
arduino-shield arduzynq fpga fpga-board rtl te0723 trenz tutorial uart vhdl vivado vivado-hls xilinx zynq-7000 zynq-7010 zynq-example-project
Last synced: 12 Mar 2025
https://github.com/fastmachinelearning/ml4fg
Machine Learning on frame grabbers for ultra-low latency in situ inference
dl dnn fpga hls imaging inference machine-learning ml vivado vivado-hls
Last synced: 14 Apr 2025
https://github.com/delhatch/mandel_hls
Using Vivado HLS to create floating point IP, used to accelerate a Zynq system. Multiple engines are instantiated.
Last synced: 02 Mar 2025
https://github.com/z1skgr/reconf-computing__hls
High Level synthesis of data transfer in Vivado, Vivado HLS
data-structures data-system embedded-c embedded-systems fifo-queue high-level-synthesis hls simulation vivado vivado-hls xilinx xilinx-vivado xilinx-zynq
Last synced: 16 Mar 2025
https://github.com/albertopirillo/logical-networks-project-2020
Implementation in VHDL of an HW component capable of recalibrating the contrast of an image stored in an external memory, using a histogram equalization algorithm.
Last synced: 21 Feb 2025
https://github.com/riyasach189/rfdc_loopback_on_rfsoc4x2
The aim of this project is to demonstrate the working of the RF Data Converter IP by analyzing and replicating a part of the official Xilinx design. The goal is to recreate the radio hierarchy using custom IPs (amplitude controller and packet generator) designed in Vitis HLS 2022.1.
adc dac jupyter-notebook pynq rfdc rfsoc4x2 vitis vitis-hls vivado-hls
Last synced: 27 Feb 2025
https://github.com/tahirzia-1/uart-transmitter-and-receiver
A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.
fpga-board fpga-programming fpga-soc nexys4ddr rtl simulation systemverilog testbench uart uart-receiver uart-transmitter uart-verilog verilog verilog-hdl verilog-project vivado vivado-hls vivado-simulator
Last synced: 04 Mar 2025
