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Projects in Awesome Lists tagged with zynq-7000
A curated list of projects in awesome lists tagged with zynq-7000 .
https://github.com/b1f6c1c4/deep-darkfantasy
Global Dark Mode for ALL apps on ANY platforms.
dark-mode dark-mode-toggle dark-theme fpga verilog verilog-hdl vivado xilinx zynq zynq-7000
Last synced: 16 Dec 2024
https://github.com/duartegalvao/arduzynq-tutorials
Simple tutorials for getting started with programming on Trenz ArduZynq boards.
arduino-shield arduzynq fpga fpga-board rtl te0723 trenz tutorial uart vhdl vivado vivado-hls xilinx zynq-7000 zynq-7010 zynq-example-project
Last synced: 18 Nov 2024
https://github.com/teddy-van-jerry/sdr-psk-fpga
Dual-Mode PSK Transceiver on SDR With FPGA
amd bpsk costas-loop demodulation fpga gardner modulation psk qpsk sdr software-defined-radio synchronization transceiver verilog vivado xilinx zynq zynq-7000 zynq-7020
Last synced: 03 Dec 2024
https://github.com/svenssonjoel/zynqshell
Shell like program to run on the Zynq while experimenting
arm bare-metal zynq zynq-7000 zynq-7010
Last synced: 18 Dec 2024
https://github.com/amamory/axis-protocol-checker
AXI stream protocol checking design
axi-stream axi4 vivado zynq-7000
Last synced: 21 Nov 2024
https://github.com/svenssonjoel/gpioperformancetestergui
Gui for a zynq based GPIO performance testing "rig".
Last synced: 18 Dec 2024
https://github.com/coldnew/zybo-templates
Basic project template for Xilinx zynq-7000 ZYBO board
Last synced: 15 Nov 2024
https://github.com/amamory/zynq-hermes-noc-demo
A demonstrator of Hermes network-on-chip communicating with the ARM processor
axi-stream axi4 network-on-chip router vivado zedboard zynq-7000
Last synced: 21 Nov 2024
https://github.com/amamory/axi_noc_counter_ip
A test IP that receives a packet from the NoC, increments its the payload, and sends the packet back to the source
axi-stream axi4 axi4-stream vhdl vivado zynq-7000
Last synced: 21 Nov 2024
https://github.com/asankasovis/bidirectional_transmitter
📡 This project was intended to develop a bidirectional transmitter and reciever device that uses Visible Light Communication (VLC) technology to transmit and recieve data from one device to another. In its basic form, data is transmitted as pulses of light where on means bit 1 and off means bit 0.
amd cora digilent fpga fpga-programming serial-communication transciever uart-protocol zynq-7000
Last synced: 08 Dec 2024
https://github.com/ematech/zynq_book_pynq-z1
Zynq Book Tutorials adapted for the Digilent PYNQ-Z1
digilent digilent-pynq-z1 fpga pynq pynq-z1 xilinx xilinx-fpga xilinx-vivado xilinx-zynq zynq zynq-7000 zynq-7020 zynq-book zynq-example-project
Last synced: 08 Nov 2024
